The authors address the issue of area-time trade off in VLSI circuits using the BILBO methodology of BIST. The issue has been dealt with in an integrated manner. Two distinct approaches, integer linear programming and graph theoretic have been presented.>

When BILBO tests are being generated and scheduled, resource conflicts between I-paths and tests present many difficulties. The authors explore: how pipelining is limited by potential internal conflicts; ways to promote pipelining during test plan generation and how to incorporate a test into a test phase already containing tests that conflict with it. They do not directly address the general problems of test plan generation or test scheduling. What is offered is insight into the difficulties that (potential) conflicts provide and techniques for handling these difficulties. The insights are primarily theoretical, but the resulting techniques could be viewed as possible extensions to existing methodologies.>

An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be applied to select the optimum number of buses in a multibus architecture. The method is illustrated with an example.>

In many applications, parallelism inherent in a computation can be exploited by using a parallel computer organization. Such organizations may suffer throughput degradation because of data dependencies. The case of no data dependencies is considered. In this case, the throughput realized is dependent on the actual manner in which the parallel computer system is organized. A comparative performance study of four models of two-processor organizations is presented. The performance evaluation is through queueing analysis or simulation, the aim being to compare their response times under different workloads. This study also indicates the possibility of switching between alternate organizations in a dynamically reconfigurable system.

A queuing model is presented for the analysis of one direction of window mechanism as used in numerous data communication control procedures e.g., X.25, HDLC and SDLC. Two models of message length are considered viz. fixed length and exponential distribution. A novel approach is used to determine an effective service time to account for possible inserted idle time while waiting for the window to reopen. A set of delay characteristics is determined for different window sizes. A minor modification of the frame format is suggested to improve on the performance of the window mechanism.

In computer architecture investigations a major interest is in the analysis of organizations which explore parallelism, and therefore, may have multiple instruction and multiple data streams (MIMD). In this paper, a MIMD structure with one shared resource is analyzed for both synchronous and asynchronous request arrivals. Although the analysis is somewhat restricted, it appears that a similar approach can be used to extend the model to more general MIMD cases. Results presented for one particular set of parameters indicate that an optimum resource replication is possible such that an optimum cost performance is achieved.

Cellular arrays for arithmetic operations usually consist of identical cells connected in an iterative or near iterative pattern. By introducing latch circuits between the rows of the array, the entire unit can be pipelined. The effect of this modification is to increase the throughput on a continuous processing basis. In most of such designs, however, the amount of hardware required for a maximally or fully pipelined array is prohibitively large. Pipeline arrays with reduced amount of intermediate latch circuits imply partially pipelined designs which of course also have a lower throughput. However, several such pipeline arrays can be operated in parallel to achieve some specified total throughput. In this correspondence this aspect is analyzed and illustrated by the design of 48-bit parallel adders.

Several algorithms for the computation of the mean value of a random variable have been analyzed. Results have shown that the two previously published techniques and a modified version of one of these, give unbiased estimates of the mean value. Furthermore, although the confidence intervals have been found to be increased in all cases, the actual increase is insignificant, while the possible speed improvements in computation can be considerable.

A cellular array is described that is capable of extracting either the square or the square root of a binary number. The mode of operation is controlled by a single-mode input line. The array is iterative in its connection pattern and is therefore suitable for large-scale integrated (LSI) implementation. Approximate time-delay expressions are derived, which show that the delays for square or square-root extraction are comparable to the, delay of published array networks.

A simple extension of Ghazala's technique yields a useful criterion of essentiality of a multiple output prime implicant. Use of such a criterion can simplify the subsequent logic minimization procedure.

An iterative array for multiplication of signed binary numbers is described. It uses controlled adder-subtractor cells. The negative numbers are in two's complement form and the product, if negative, is also available in this form without requiring any additional operations.

An alternative cellular array design is described for nonrestoring extraction of square roots. The array uses a single type of adder/ subtractor cell with a near-iterative connection pattern.