In the nanometer era, process, voltage, and temperature variations are dominating circuit performance, power, and yield. Over the past few years, statistical optimization methods have been effective in improving yield in the presence of uncertainty due to process variations. However, statistical methods overconsume resources, even in the absence of variations. Hence, to facilitate a better performance-power-yield trade-off, techniques that can dynamically enable variation compensation are becoming necessary. In this article, we propose a dynamic technique that controls the instance of data capture in critical path memory flops, by delaying the clock edge trigger. The methodology employs a dynamic delay detection circuit to identify the uncertainty in delay due to variations and stretches the clock in the destination flip-flops. The delay detection circuit uses a latch and set of combinational gates to dynamically detect and create the slack needed to accommodate the delay due to variations. The Clock Stretching Logic (CSL) is added only to paths, which have a high probability of failure in the presence of variations. The proposed methodology improves the timing yield of the circuit without significant overcompensation. The methodology approach was simulated using Synopsys design tools for circuit synthesis and Cadence tools for placement and routing of the design. Extraction of parasitic of timing information was parsed using Perl scripts and simulated using a simulation program generated in C++. Experimental results based on Monte-Carlo simulations on benchmark circuits indicate considerable improvement in timing yield with negligible area overhead.

Optical flow computation in vision-based systems demands substantial computational power and storage area. Hence, to enable real-time processing at high resolution, the design of application-specific system for optic flow becomes essential. In this paper, we propose an efficient VLSI architecture for the accurate computation of the Lucas-Kanade (L-K)-based optical flow. The L-K algorithm is first converted to a scaled fixed-point version, with optimal bit widths, for improving the feasibility of high-speed hardware implementation without much loss in accuracy. The algorithm is mapped onto an efficient VLSI architecture and the data flow exploits the principles of pipelining and parallelism. The optical flow estimation involves several tasks such as Gaussian smoothing, gradient computation, least square matrix calculation, and velocity estimation, which are processed in a pipelined fashion. The proposed architecture was simulated and verified by synthesizing onto a Xilinx Field Programmable Gate Array, which utilize less than 40% of system resources while operating at a frequency of 55 MHz. Experimental results on benchmark sequences indicate 42% improvement in accuracy and a speed up of five times, compared to a recent hardware implementation of the L-K algorithm.

In the nanometer regime, the effects of variations are having an increasing impact on the delay, power, and yield characteristics of devices. In this paper, we propose the use of fuzzy and stochastic mathematical programming techniques for variation aware timing-based incremental placement. The uncertainty due to process variations in these techniques, are modeled using fuzzy numbers and probabilistic constraints, respectively. The objective is to minimize the critical path delay of the circuit in the presence of variations considering gate and interconnect delays. In the fuzzy approach, the average and worst case deterministic optimizations are performed to identify the bounds and convert the uncertain fuzzy problem into a crisp nonlinear problem. The stochastic optimization framework, on the other hand, transforms the probabilistic constraints into a second-order conic program (SOCP) with explicit mean and variance values. The fuzzy and stochastic approaches tested on ITC'99 benchmark circuits yielded around 12.60% and 10.53% improvements in timing, when compared to optimization with the worst case process variations setting.

The computation of optical flow in video sequences is a challenging task in most camera based scene interpretation systems. In the past, most optical flow computation algorithms has been either implemented in software running on general purpose processors or designed as an application specific hardware. However, these implementations either cannot support real-time processing requirements or result in excessive inaccuracies in the computed velocity values. In this work, we propose a efficient VLSI system architecture for computing the optical flow in video sequences using the Lucas-Kanade (L-K) algorithm. The algorithm is converted into high speed RTL implementation by exploiting the inherent paralellism in the data flow graph. Clever pipelining strategies has been used throughout the design to further improve the speedup of velocity computation. We have mapped the RTL design on a Xilinx Virtex II Field Programmable Gate Arrays (FPGA) supported with Kingston DIMM DDR memory module, and a Pixel-Plus 2.0 Mega-pixel camera on the XUPV2P FPGA board. Experimental results of our proposed design showed significant improvements in accuracy with a speedup of five times when compared with other recent hardware implementations.

The aggressive scaling of technology has not only accentuated the effects of intradie parametric variations in devices, but it has also impacted the effects of optimizing a certain performance metric on the optimality of other metrics. Thus, there is a need for optimization methods that can perform the simultaneous optimization of multiple metrics considering the effects of process variations. In this article, a novel variation-aware gate sizing framework has been developed that can perform simultaneous optimization of multiple performance metrics. In this framework, the relationships between the optimization metrics (like dynamic power, leakage power, and crosstalk noise) are modeled as a function of the gate sizes in the objective function. The delay values obtained from unconstrained delay optimization and the noise margins derived from coupling capacitance information form the constraints for the multimetric optimization problem. As an abstract framework, it is independent of the type of mathematical programming approach as well as the metrics chosen to be optimized. The framework has been implemented using a mathematical programming approach and has been tested on ITC'99 benchmarks for different combinations of multimetric and single-metric optimizations of delay, dynamic power, leakage power, and crosstalk noise. The results indicate that the framework identifies good solution points, and is efficient for postlayout optimization via gate sizing.

Technology scaling has not only magnified the effects of device process variations, but it has also precipitated the need for simultaneous optimization of several performance metrics. In this paper, we propose a novel gate sizing approach for multi-metric optimization of delay, power, and crosstalk noise. The algorithm is based on the concepts of mathematical programming, and models the process variation uncertainty considering spatial correlations. The approach identifies leakage power, dynamic power, and crosstalk noise as the objectives, and the optimized gate delays are kept as constraints. Initially, the deterministic upper and lower bounds of the objectives are identified, and during the final step, a crisp non-linear programming problem is formulated using these boundary values. The problem is solved using KNITRO, an interior-point based optimization solver. The proposed model maximizes the variation resistance, thus providing higher yield. ITC'99 benchmarks were used to test the proposed approach, and the results indicate that our algorithm identifies the solution points that are closest to the nominal bounds, while maintaining high timing yield.

Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact on the yield of the integrated circuits and need to be considered early in the design flow. Traditional corner based deterministic methods are no longer effective and circuit optimization methods require reinvention with a statistical perspective. In this paper, we propose a new gate sizing algorithm using fuzzy linear programming in which the uncertainty due to process variations is modeled using fuzzy numbers. The variations in gate delay which is a function of the gate sizes and the fan-outs of the gates are represented using triangular fuzzy numbers with linear membership functions. Initially, as a preprocessing step for fuzzy optimization, we perform deterministic optimizations by fixing the fuzzy parameters to the worst and the average case values, the results of which are used to convert the fuzzy optimization problem into a crisp nonlinear problem. The crisp problem with delay and power as constraints is then formulated to maximize the robustness, i.e., the variation resistance of the circuit. The fuzzy optimization approach was tested on ITC'99 benchmark circuits and the results were validated for timing yield using Monte Carlo simulations. The proposed approach is shown to achieve better power reduction than the worst case deterministic optimization as well as the stochastic programming based gate sizing methods, while having comparable runtimes.

Increasing dominance of process variations in the nanometer designs are posing significant challenges for circuit design and optimization. The variations in parameters such as channel length and the gate oxide thickness impacts circuit delay and power. In this paper, we propose a new gate sizing algorithm using fuzzy mathematical programming (FMP) in which the uncertainty due to process variations is modeled using fuzzy numbers. The variations in gate delay, which is a function of gate sizes and the fan-outs of the gate, are represented using triangular fuzzy numbers with linear membership functions. The variation aware gate sizing problem is formulated as a fuzzy mathematical program to perform a delay constrained power minimization in the presence of variations. Initially, a deterministic optimization is performed by fixing the fuzzy parameters to the worst and the average case values and the results are used to convert the fuzzy optimization problem into a crisp non-linear problem which is then solved using a non-linear optimization solver. The above model with delay and power as constraints, maximizes the robustness, i.e., the variation resistance of the circuit and thus the yield. The proposed approach was tested on ISCAS '85 benchmarks and the results were validated for timing yield using monte-carlo simulations. The fuzzy approach yields significantly better results compared to stochastic programming based gate sizing approach with a comparable runtime.

Logarithmic number systems (LNS) offer a viable alternative in terms of area, delay, and power to binary number systems for implementing multiplication and division operations for applications in signal processing. The Mitchell algorithm (MA), proposed, reduces the complexity of finding the logarithms and the antilogarithms using piecewise straight line approximations of the logarithm and the antilogarithm curves. The approximations, however, result in some loss of accuracy. Thus, several methods have been proposed in the literature for improving the accuracy of Mitchell's algorithm. In this work, we investigate a new method based on operand decomposition (OD) to improve the accuracy of Mitchell's algorithm when applied to logarithmic multiplication. In the OD technique proposed, for reducing the amount of switching activity in binary multiplication, the two inputs to be multiplied are together decomposed into four binary operands and the product is expressed as the sum of the products of the decomposed numbers. We show that applying operand decomposition to the inputs as a preprocessing step to Mitchell's multiplication algorithm significantly improves the accuracy. Experimental results indicate that the proposed algorithm for logarithmic multiplication reduces the error percentage of Mitchell's algorithm by 44.7 percent on the average. It is also shown that the OD method yields further improvement when combined with the other correction methods proposed in the literature

The focus of this paper is to present a bit transition count analysis for various error detection and correction (EDAC) schemes through a detailed simulation. The simulation also brings out the impact of various EDAC schemes - linear, BCH, m-out-of-n, Berger and SEC-MUED - on bit transition count with respect to number of FSM partitions under different partitioning objective functions for low power. A decrease up to 30 percent in bit transitions count under the three partitioning objectives has been observed.