This paper presents a lightweight background calibration for the distortion of the analog-to-digital converter (ADC)’s input buffer. The buffer’s nonlinearity is calibrated on-chip by the Harmonic-Compensated Diode Load (HC-DL), whose bias voltage is determined by the calibration algorithm facilitated by dither injection at the input of the buffer. A two-step ADC is exploited to demonstrate the calibration, where the coarse-fine ADC gain mismatch and sampling skew at the 1ststep are calibrated by monitoring the occupation of the correction range (OCR) at the 2ndstep. Verified in a 12b 1 GS/s pipe-SAR ADC in 28 nm CMOS, the SNDR and SFDR at Nyquist input are 60.96 dB/76.8 dB, respectively and the SFDR keeps >75 dB over PVT.

This work presents an always-on CNN processor featuring compute-in-memory (CIM) and layer-fusion (LF) techniques. It demonstrates an end-to-end neural network (NN) inference while eliminating memory accesses for both the weight and inter-layer activation, thus significantly saving associated energy. The analog LF-CIM processor combines charge- and time-domain multiply-accumulate (MAC) arrays in a fusional manner, avoiding the need for the interfacial analog-to-digital and digital-to-analog converters; it also supports a highly sparsity-adaptive network and exhibits low-voltage-supplied tolerance to circuit noise and variations, which facilitates an energy-efficient and robust CNN processor, simultaneously. Furthermore, the full-precision activation originating from the LF reduces the NN parameters and operations, while the inference accuracy is improved by the presented ensemble NN. The prototype processor is fabricated in a 28-nm CMOS process, demonstrating a fully on-chip MNIST inference with 97.9% accuracy. It operates at 3,508 frames per second while consuming$11.6~\mu $W at a 0.5-V supply; the achieved efficiency of 3.32 nJ/frame is over 50-fold than the state-of-the-art end-to-end MNIST accelerators.

Compute-in-memory (CIM) is a promising approach for realizing energy-efficient deep neural network (DNN) accelerators. Previous CIM works focusing on uniform quantization (UQ) demonstrated a higher Multiply-accumulate (MAC) precision requirement to maintain DNN inferencing accuracy, resulting lower energy efficiency. The nonuniform quantization (NUQ) has proved to require lower precision than UQ, while the existing implementations are based on high precision digital lookup table (LUT) (e.g., 16-bit), leading to large energy and area overhead for multiplier. This work presents CLUT-CIM fabricated under 28-nm CMOS featuring: 1) a capacitance LUT (CLUT)-based NUQ MAC circuit with thermometer coding scheme for weight and input activation that avoids digital LUT and reduces the energy and area overhead; 2) a signed-channel training (SCT) method that reduces the switching activity of computation to improve the energy efficiency; 3) a dual-port 6T-SRAM array to enable simultaneously weight updating and CIM operations, enhancing the memory utilization and CIM throughput. Under 3-bit NUQ precision, the peak energy efficiency is 114.3 TOPS/W, and peak throughput density is 31.78 TOPS/mm2.

A 12-bit, 1-GS/s SAR-assisted pipeline ADC with background distortion and split-ADC-like gain calibrations is presented. The ADC includes an input buffer where its distortion is tackled by calibration. A low-cost auxiliary channel is introduced that serves as a reference for the calibration. It employs only a quarter of the input swing of the main channel, thus achieving adequate linearity. The auxiliary channel is further utilized for the gain calibration, where a split-ADC-like calibration is proposed to ease residue amplifier design constraint. The coefficients in the digital post-distortion filter are iterated through a multi-step multi-layer LMS algorithm, which converges faster and is more robust than its single-step counterpart. The buffered ADC works under a 1 V power supply thanks to the calibration, consuming 19.2 mW, where the input buffer contributes 18% of the total power. The calibration improves the SFDR by >14 dB within the 1st Nyquist zone, and >8dB up to 4th Nyquist input zone. The design achieves 59.3 dB SNDR and 67.1 dB SFDR at Nyquist input. The entire calibration converges within$1\times 10 ^{5}$iterations.

This paper presents a fast transient response flipped voltage follower (FVF) low-dropout regulator (LDO) for high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs), enabled by a direct-coupled auxiliary loop (DC-AL) with replica load. The proposed auxiliary loop consists of an additional power MOS directly controlled by a replica load, which imitates the response of the main loop but scaled down for low power and compact area. This low die cost solution enables a fast transient response from the LDO that well suits a high-speed SAR ADC. The concept, verified in a 12bit VCM-based SAR ADC in 65nm CMOS, operates at 100 MS/s under a 1.2 V supply. The simulation results demonstrate that the DC-AL scheme improves the worst-case DNL and INL from 2.05/-1 LSB and 1.91/-1.83 LSB to 0.43/-0.46 LSB and 0.56/-0.52 LSB, respectively. The LDO with the DC-AL as the reference buffer consumes 0.65 mW with only 0.5 pF of decoupling capacitance, while the DC-AL spends only 0.08 mW.

This paper presents a supply-noise-robust PLL that achieves low-jitter performance within full-spectrum supply interference. A digital-regulated supply noise cancellation (DSNC) scheme suppresses the large amplitude supply noise within an adequate range for a supply-noise-insensitive (SNI) VCO. It ensures that the low pushing factor SNI-VCO only induces a decent amount of phase noise falling within the effective correction range of the phase noise cancellation (PNC). A sample-and-isolate-based (S/I)-PNC cascaded at the VCO output enables a wider correction range for a fine supply noise and phase noise suppression. Fabricated in 28-nm CMOS with an area of 0.088 mm2, the proposed PLL consumes 6.65 mW from a 1 V supply at 4 GHz output. With 20 mVpp supply interference, the prototype obtains a maximum >37 dB output spur reduction at 5 MHz and maintains ≤1.6 ps RMS jitter in the worst case. The suppression performance degrades less than 10% within −20 °C to 80 °C operation temperature.

This paper presents an entropy-source-preselection-based strong PUF (ESP-PUF). Through the presented entropy-source-preselection scheme, we will convert first the input challenge bits of the ESP-PUF into the entropy selection signals through the front-end selection network, realized based on an XOR tree. Then the entropy selection signals serve as the power-on indicator to randomly select the back-end entropy sources to generate the raw responses. Utilizing this preselection scheme, we can fulfill both ultra-low power and strong resilience to machine learning (ML) attacks. An effective randomness-enhancement block amplifies the randomness of the raw responses thus alleviating their bias. Moreover, we propose an obfuscation-based protection mechanism to further protect the root challenge-response pairs (CRPs) of the entropy sources and enhance the resilience to ML attacks. Fabricated in 65nm CMOS LP technology, the proposed ESP-PUF shows a high energy efficiency of 0.46pJ/bit. Meanwhile, it demonstrates an average bit-error rate (BER) of 5.83% in the worst-case for the temperature range of −20°C to 120°C and a supply voltage variation of ±10%. The proposed CRPs filtering method can suppress the worst-case BER to a value$< 6.7\times 10 ^{-6}$, presenting high stability. The proposed ESP-PUF occupies an active area of 0.0122 mm2. After training for 1M CRPs samples, the prediction accuracy of the adopted ML algorithms is still ~50%, confirming a strong resilience of the proposed ESP-PUF.

This paper presents a weak PUF-assisted strong PUF that combines the metrics between weak and strong PUFs. Unlike the conventional strong PUFs that rely on the nonlinear combination of a large number of entropy cells for high modeling attacks resilience, the presented strong PUF utilizes unique key streams to bitwise encrypt the raw responses from the conventional strong PUF to facilitate an inherent immunity to modeling attacks thus fulfilling high-level security. A device-specific pseudo-random number generator (P-RNG) configured by a dedicated weak PUF array generates a unique key stream (K). Since the weak PUFs are inherently immune to machine learning or deep learning-based modeling attacks, the final encrypted responses of the proposed strong PUF are also inherently immune to modeling attacks. Moreover, we propose a two-to-one (2-to-1) selection scheme and the digitally-controlled-delay-line (DCDL)-based stability checker to suppress the bit-error-rate (BER) of the weak PUF array and improve the efficiency of the spatial majority voting (SMV)-based error correction scheme, thus achieving high stability for our proposed strong PUF. Fabricated in 65nm CMOS GP technology, the proposed weak PUF-assisted strong PUF shows a high energy efficiency of 3.05 pJ/bit at a 2M bit rate. Meanwhile, it demonstrates an ultra-low average worst-case BER of$8.9 \times 10^{-11}$for the temperature range of −20°C to 120°C and a supply voltage variation of ±10% with the proposed stabilization schemes. The proposed strong PUF occupies a core area of 0.075mm2.

This paper proposes a 3rdorder continuous-time delta-sigma modulator (CTDSM) with a single amplifier biquad (SAB) and excess loop delay (ELD) merged integrator. The integrator enables a 2ndorder noise-shaping together with ELD compensation with just a single Opamp and feedback DAC. A three-stage Opamp with a hybrid frequency-compensation scheme is presented, which achieves high gain and large unity-gain bandwidth (UGBW) with low power. The circuit secures an extra order noise-shaping through a passive noise-shaping SAR (NS-SAR) quantizer (QTZ) while further incorporating a preliminary sampling and quantization (PSQ) technique, the 1storder NS QTZ can run at 1.5 GHz with 6b. The design, implemented in 28 nm, obtains 74.4 dB SNDR with 50 MHz bandwidth while consuming 10.4 mW from 1.5 V and 1 V power supplies. The prototype attains a dynamic range of 80.6 dB with a Schreier FOM of 171.2 dB. With the presented integrator and Opamp, the loop filter only consumes 14 % of the total DSM power consumption.

This paper presents a two-way time-interleaved (TI) 7-bit 2-GS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The design achieves wideband operation with an effective resolution bandwidth (ERBW) in the 3rdNyquist zone. The converter's front-end employs current integrating (CI) sampler that provide both buffering and anti-alias (AA) filtering at low power dissipation. Facilitated by the CI-samplers' inherent inter-sample interactions, the timing mismatch among the TI channels can be detected in the amplitude domain, obviating the need for a dedicated reference channel for background calibration. After calibration, the ADC achieves 36.4 dB signal-to-noise-and-distortion ratio (SNDR) near Nyquist and >2.6 GHz ERBW at a sampling rate of 2 GS/s. The ADC's power consumption is 7.62 mW (including the CI buffer) and its Walden figure of merit (FoMw) is 70.8 fJ/conversion-step.

This paper presents an input correlated swap-sampling (ICSS) technique, which correlates the initial voltage of the sampling capacitor with the incoming input signal before the sampling phase; therefore, significantly reducing the power dissipation of the input driver. The concept can be easily implemented in a two-step conventional SAR ADC that costs a negligible circuit overhead and extra power consumption. According to theoretical analysis, the proposed ICSS scheme saves up to 77.8% or 12.3% power of the input driver when compared to conventional or recently reported works, respectively. The ICSS approach has been verified in a 12 bits SAR ADC in 28 nm CMOS, operating at 25 MS/s under 0.9 V supply. The simulation results demonstrate that the ADC achieves a signal-to-noise distortion ratio (SNDR) of 67.3dB @ Nyquist frequency, leading to a FoM of 3.4 fJ/conv.step.

This brief presents a time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) with an improved variance-based time-skew estimation technique, where we introduce a window detector (WD) based on a SAR ADC. It brings low hardware overhead and 104times faster convergence speed when compared to the prior variance-based time-skew calibration. Postlayout simulation results of a 10-bit, 2-GS/s TI-ADC in 28-nm CMOS process verify the effectiveness of the proposed calibration. The results indicate that the signal noise and distortion ratio/spurious free dynamic range of the ADC improved from 41.9/48.6 to 53.2/63.3 dB after calibration. The total area and power are 0.105 mm2and 14.9 mW, respectively, where the WD occupies 0.0015 mm2and 0.55 mW.

This brief reports a passive noise-shaping (PNS) scheme for successive approximation register (SAR) analog-to-digital converter (ADC) based on the two-step integration with passive gain and comparator gain techniques. The analysis shows that the proposed method achieves a better noise-shaping (NS) efficiency than prior arts, which enhances the noise attenuation by 14 dB. A design example is provided which further adopts the delta-sampling technique to relieve the conversion efficiency loss due to the oversampling in the NS SAR ADC. The efficiency of the proposed PNS scheme and the performance of the ADC are verified by simulation achieving a 13.2 effective number of bits with a 10-b ADC architecture and eight conversion cycles for a signal bandwidth of 2 MHz sampled at 100 MS/s. The calculated Schreier figure of merit (FoM) and Walden FoM are 176.8 dB and 16 fJ/conv.-step, respectively.

A 10-bit 500-MS/s partial-interleaving pipelined successive approximation register (SAR) analog-to-digital converter (ADC) architecture is presented that implements a full-speed 2-bit/cycle SAR at the front end with interleaved residue MDACs and SAR ADCs at the back end. This architecture achieves high speed, while preventing the interleaving spurs. In addition, the design considerations and calibration techniques for gain and offset are also introduced. A histogram stage gain error (HSGE) calibration is implemented to correct the conversion nonlinearities in the digital domain. Measurement results on a 65-nm CMOS prototype show an signal-to-noise distortion ratio (SNDR) of 55.9 dB at dc input and a figure of merit (FoM) of 32 fJ/conversion step at 1.2 V supply.

This paper discusses the use of a low gain amplifier and a passive switched-capacitor (SC) network to enable the SC integrator function. The method is applied to a delta-sigma modulator to achieve high resolution as proved by the 65-nm CMOS technology test vehicle. Compared with the conventional operational amplifier (op-amp)-based SC integrator, this solution utilizes a low-gain open-loop amplifier to drive a passive SC integrator with positive feedback. Since the open-loop amplifier requires a low dc gain and implements an embedded current adder, the power consumption is very low. Power reduction for single bit is obtained by using passive feedforward with built-in adder to assist the first amplifier. The low swing obtained at the output of the active blocks relaxes the slew rate requirement and enhances the linearity. Implemented in 65-nm digital CMOS technology with an active area of 0.1 mm2, the test chip achieves a dynamic range of 91 dB, peak signal-to-noise ratio of 88.4 dB, peak signal-to-noise-plus-distortion ratio of 88.2 dB, and a spurious free dynamic range of 106 dB while consuming 73.6 μW in a 25-kHz signal bandwidth at 1 V supply, yielding a FoMWaldenof 70 fJ/conv-step and FoMSchreierof 176 dB.

This brief presents a 7-bit 700-MS/s four-way time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC). A partial Vcm-based switching method is proposed that requires less digital overhead from the SAR controller and achieves better conversion accuracy. Compared with switchback switching, the proposed method can further reduce the common mode variation by 50%. In addition, the impacts of such a reduction on the comparator offset, noise, and input parasitic are theoretically analyzed and verified by simulation. The prototype fabricated in a 65-nm CMOS technology occupies an active area of 0.025 mm2. The measurement results at the 700 MS/s sampling rate show that the ADC achieves signal-to-noise-and-distortion ratio of 40 dB at Nyquist input and consumes 2.72 mW from a 1.2 V supply, which results in a Walden FoM of 48 fJ/conversion step.

This brief reports a 120 MS/s 12-bit successive approximation register analog-to-digital converter (ADC). The conversion nonlinearity in a bridge digital-to-analog converter is analyzed, and its corresponding histogram-based ratio mismatch (HBRM) calibration is presented in detail. Verified by behavioral simulations as well as measured results, the solution improves both the dynamic performance and the static performance of the ADC. The measurement results demonstrate that the HBRM calibration effectively improves the signal-to-noise distortion ratio from 56.9 to 63.7 dB at dc input, with a sampling frequency of 120 MS/s.

This brief presents a uniform quantization theory (UQT)-based digital-to-analog converter (DAC) linearity calibration for a successive approximation register (SAR) analog-to-digital converter. According to the uniform quantization noise property, the nonlinearity due to the parasitics in an LSB array of the split-DAC structure is estimated and corrected in the digital domain. The calibration requires that the characteristic of the input signal must fulfill the prerogative of the quantization theory. The advantages lie in its low design complexity with no additional analog circuit modification. The proposed calibration is verified by both behavioral simulations and measured results in an SAR ADC. The measurements are based on a prototype implemented with large nonlinear split-DACs, which demonstrate that the UQT-based linearity calibration can effectively improve the Signal to Noise and Distortion (SNDR) from 56.9 to 63.3 dB at dc input with a sampling frequency of 120 MS/s.

This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyzed hereunder. In addition, a code-randomized calibration technique is proposed to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulations, as well as measured results. Performances of both switching methods are demonstrated in 90 nm CMOS. Measurement results of power, speed, and linearity clearly show the benefits of using Vcm-based switching.

This paper presents a monotonic multi-switching technique that is implemented in a 8b SAR ADC. The proposed switching reduces 1/2 total DAC capacitance and achieves more than 80% switching energy saving when compared to the most advanced VCM-based or merged capacitor switching methods. Besides, conversion redundancies are added to compensate the errors resulting from insufficient DAC settling and reference noise. The proposed 8-bit SAR ADC operates at 100MS/s with 0.6V supply in 65nm CMOS. The simulation results show that the design achieves 48.8dB SNDR with only 0.524mW power. The Figure-of-Merit (FoM) is 23.35fJ/conversion-step.

A voltage feedback charge compensation technique is presented to prevent the conversion nonlinearity due to the parasitic effect of split capacitive DAC structure in successive approximation register (SAR) ADCs. The charge compensation is achieved by using an open loop amplifier that performs voltage feedback to the DAC array via a compensation capacitor, which is easy to be implemented with very low power dissipation. The technique is utilized in the design of a 10b 80MS/s SAR ADC in 65-nm CMOS technology. The simulation results show that the proposed charge compensation technique can improve the Effective Number of Bits (ENOB) from 8.3bits to 9.6bits and differential/integral nonlinearity from 3LSB/1.65LSB to 0.45LSB/0.74LSB respectively with only 300 uW power dissipation in the proposed charge compensation circuitry.

Recently, support vector machines (SVMs) have been engaged on relevance feedback tasks in content-based image retrieval. Typical approaches by SVMs treat the relevance feedback as a strict binary classification problem. However, these approaches do not consider an important issue of relevance feedback, i.e. the unbalanced dataset problem, in which the negative instances largely outnumber the positive instances. For solving this problem, we propose a novel technique to formulate the relevance feedback based on a modified SVM called biased support vector machine (Biased SVM or BSVM). Mathematical formulation and explanations are provided for showing the advantages. Experiments are conducted to evaluate the performance of our algorithms, in which promising results demonstrate the effectiveness of our techniques.