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Robert Bencivenga

dblp:87/4477 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.011991
Enhanced Controllability for IDDQ Test Sets Using Partial Scan · DAC 1991
Electronic design automation › hardware verification and test › fault testing
IDDQ testing		 0.011991
Enhanced Controllability for IDDQ Test Sets Using Partial Scan · DAC 1991
Electronic design automation › hardware verification and test › design for testability › scan design
partial scan		 0.011991
Enhanced Controllability for IDDQ Test Sets Using Partial Scan · DAC 1991
Electronic design automation › hardware verification and test
test generation		 0.011991
Enhanced Controllability for IDDQ Test Sets Using Partial Scan · DAC 1991
Electronic design automation › hardware verification and test
design for testability		 0.011991
Enhanced Controllability for IDDQ Test Sets Using Partial Scan · DAC 1991
Electronic design automation › hardware verification and test › design for testability
scan design		 0.011991
Enhanced Controllability for IDDQ Test Sets Using Partial Scan · DAC 1991

Methods — techniques the papers use, named apart from their topics

partial scan · 0.0
YearPublicationVenuePosition
1991 Enhanced Controllability for IDDQ Test Sets Using Partial Scan
Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin
 DAC3