High temperature or temperature nonuniformity has become a serious threat to performance and reliability of high-performance integrated circuits (ICs), which makes the thermal effect turn into a nonignorable issue in the circuit design or the physical design. In order to estimate temperature accurately, the locations of modules have to be determined in advance, which makes an efficient and effective thermal-aware floorplanning play a more important role. Hence, this article proposes a differentiable nonlinear placement model that can optimize temperature and minimize wirelength at the same time without needing to construct a congestion map. In addition, to avoid inducing longer wirelength while optimizing temperature, we propose some techniques, such as thermal-aware clustering, shrink of hot modules, or thermal-force modulation in the multilevel framework. The experimental results demonstrate that temperature and wirelength are greatly improved by our method compared to Corblivar. More importantly, our runtime is quite fast and the fixed-outline constraint can also be satisfied.

High temperature or temperature nonuniformity has become a serious threat to performance and reliability of high-performance integrated circuits (ICs). Since the temperature in a 3-D IC is mainly determined by a power distribution across tiers, this article proposes a novel method to allocate modules to tiers while exploring a better power distribution according to the hyperparameter optimization technique. In addition, we integrate the sub-3-D thermal mask into the analytical formulation to interleave high power consumption modules in contiguous tiers during distributing modules over placement regions so that it is possible to insert through-silicon vias (TSVs) around high power modules to further reduce the temperature at a later stage. Since the temperature in a tier will be changed every time the locations of TSVs in its lower tier are moved, we also propose a procedure to update the temperature map before refining locations of TSVs. Experimental results have demonstrated that the proposed methodology can effectively reduce the temperature of a 3-D IC with a slight increase in the wirelength. Moreover, its runtime is quite fast.

Today, secure systems are built by identifying potential vulnerabilities and then adding protections to thwart the associated attacks. Unfortunately, the complexity of today's systems makes it impossible to prove that all attacks are stopped, so clever attackers find a way around even the most carefully designed protections. In this article, we take a sobering look at the state of secure system design, and ask ourselves why the “security arms race” never ends? The answer lies in our inability to develop adequate security verification technologies. We then examine an advanced defensive system in nature – the human immune system – and we discover that it does not remove vulnerabilities, rather it adds offensive measures to protect the body when its vulnerabilities are penetrated We close the article with brief speculation on how the human immune system could inspire more capable secure system designs.

In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In this paper, we use adjustable delay buffers (ADB) whose delays can be tuned or adjusted to minimize clock skew under different power modes. Assuming that the positions of$k$ADBs are already determined, we first propose a linear-time optimal algorithm which assigns the values of ADBs so that the skew is optimal among all possible ADB assignments with a possibility of latency penalty. Then, we propose a modified optimal algorithm without latency penalty. We also propose an efficient heuristic to determine good positions for ADBs. Our results show significant improvement when compared to cases without ADBs.

In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In this paper, we use Adjustable Delay Buffers (ADB) whose delays can be tuned or adjusted to minimize clock skew under different power modes. Assuming that the positions of k ADBs are already determined, we propose a linear-time optimal algorithm which assigns the values of ADBs so that the skew is optimal among all possible ADB assignments. We also propose an efficient heuristic to determine good positions for ADBs. Our results show significant improvement when compared to cases without ADBs. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids — Optimization General Terms: Algorithms, Reliability

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25degC in the silicon chip. Moreover, it can achieve ESD robustness of over 8 kV in human-body-model (HBM) and 750 V in machine-model (MM) ESD tests, respectively.

In this work, we propose a hardware-sharing P-MBIST design to test multiple memory instances with different types in one BIST design. By sharing a common address generator and controller, the area overhead is significantly reduced in comparison to existing works. A high-speed address generator with column-scan feature is also proposed for at-speed/full-speed tests. The proposed P-MBIST design can be automatically generated according to a user-defined configuration file. A priority-based verification process for the soft IP is also presented in this work.

The crosstalk fault becomes more and more important in the deep submicron SoC and its detection involves sophisticated timing measurement. In this paper, a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed. The scheme, without using timing measurement, applies a transition on the aggressor line and a critical width pulse, CWP, to the victim line and detects the propagation of the CWP at the output of the victim line. The scheme is simple and simulation analysis and experiments show that it is effective in detecting crosstalk faults.

With the advent of deep submicron technology and system-on-chip (SOC) design methodology, we are seeing on-chip memory cores to represent a growing percentage of the chip area. The yield of an SOC is usually dominated by the memory yield, so the improvement of memory yield is crucial in SOC development. In this work, we propose a built-in self-repair (BISR) scheme for memory yield improving. The novelty of our approach is that we can identify the fail patterns so that appropriate spare elements (e.g., spare rows, columns, words, or blocks) can be allocated to repair the defective memory. Some BISR methods are discussed and compared. We select the scheme that uses fewer spare elements than others given the same repair rate. The area overhead of the BISR scheme is only 2.2% for an 8K/spl times/64 memory.

With the advent of system-on-chip (SOC), the demand for embedded memory cores increases rapidly. The magnetic random access memory (MRAM) is considered one of the potential candidates that replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM has a high speed and does not need high supply voltage for read/write operations, so it has the advantages of RAM and flash memory, making it a potentially good choice for SOC. The testing of MRAM, however, has not been fully investigated. In this work we classify and analyze the MRAM defects and their behavior, and propose its fault models. We have built a SPICE model of MRAM cell and performed defect injection and simulation of a real MRAM circuit. The circuit has been implemented and fabricated with a novel 0.18 m technology. The simulation results regarding the correlation between the defects and conventional fault models show that most of the defects can be covered by the stuck-at fault model. The test data based on the fabricated chips show that the stuck-at faults do cover most of the defects on the chips. However, from the experiment we also have identified two new faults, i.e., the Multi-Victims fault and Kink fault.