In this paper, I present a CMOS differential-difference amplifier (DDA) circuit with a pair of matched class-AB input stages that each produce a differential output current that is an odd-symmetric, expansive nonlinear function of its differential-mode input voltage. In contrast to those of the usual differential pair, the nonlinear current-voltage characteristics of these class-AB transconductors do not saturate and allow the proposed DDA circuit to function properly with a differential-mode input voltage range that is comparable to the transconductor's common-mode input voltage range. I show experimental measurements from a proof-of-principle prototype circuit breadboarded from transistor arrays that were fabricated in a 500-nm CMOS process through MOSIS.

In this paper, I present a simple CMOS bump circuit whose transfer characteristic width is electronically adjustable via a single back-gate bias voltage. The proposed circuit comprises two asymmetric differential pairs whose transfer characteristics can be shifted left and right about the origin by adjusting this back-gate bias. One output current from each diff pair is fed into a current correlator circuit, which produces the bump current. The circuit can simultaneously produce a complementary antibump current by summing the other two diff pair currents. I describe the proposed circuit's operation, present a large-signal analysis for weak-inversion bias currents, and show measurements from a proof-of-principle prototype made from commercially available MOS transistor arrays.

This paper describes an event-based binaural silicon cochlea aimed at spatial audition and auditory scene analysis. The chip has a matched pair of 64-stage cascaded analog second-order filter banks with 512 pulse-frequency modulated (PFM) address-event representation (AER) outputs. The spectral selectivity is sharpened through 2 different on-chip methods: an on-chip local Q DAC and an on-chip spatial sharpening through nearest neighbour lateral inhibition. The fabricated chip in a 4-metal 2-poly 0.35um CMOS process consumes peak 25mW power for the digital circuits and 33mW for the analog core. Dynamic range to produce PFM output is 36dB (25mVpp to 1500mVpp at microphone preamp output). Event timing jitter is 2us for 250mVpp input. The peak output bandwidth is 10M events per second (eps) but typical speech scenarios show rates of 20keps.

In this paper, we present a simple class-AB CMOS transconductor, which is based on Delbriick's bump/antibump circuit, whose differential output current is an expansive nonlinear function of its differential-mode input voltage. We describe the operation of the new transconductor qualitatively and derive an analytical model of its output currents from the Enz-Krummenacher-Vittoz (EKV) model of the MOS transistor. We also provide experimental measurements of the DC transfer characteristics of a version of the circuit that was fabricated in a 0.5-mum CMOS process through MOSIS.

We propose an analog VLSI approach to implementing the projection neural networks adapted for the support vector machine with radial-basis kernel functions, which are realized by a proposed floating-gate bump circuit with the adjustable width. Other proposed circuits include simple current mirrors and log-domain filters. Neither resistors nor amplifiers are employed. Therefore it is suitable for large-scale neural network implementations. We show the measurement results of the bump circuit and verify the resulting analog signal processing system on the transistor level by using a SPICE simulator. The same approach can also be applied to the support vector regression. With these analog signal processing techniques, a low-power adaptive analog system without any analog-to-digital convertor but with the capability of learning, classifying, and regressing becomes feasible.

In this paper, we describe three simple low-voltage CMOS analogs of the Wilson current mirror that function well at all current levels, ranging from weak inversion to strong inversion. Each of these current mirrors can operate on a low power-supply voltage of a diode drop plus two saturation voltages and features a wide output-voltage swing with a cascode-type incremental output impedance. Two of the circuits requires an input voltage of a diode drop plus a saturation voltage while the third one features a low input voltage of a saturation voltage. We present experimental results from versions of these three current mirrors that were fabricated in a 0.5-μm CMOS process through MOSIS, comparing them with CMOS implementations of the conventional Wilson and super-Wilson current mirrors.

A procedure for synthesizing multiple-input translinear element (MITE) networks that implement a given system of translinear-loop equations (STLE) is presented. The minimum number of MITEs required for implementing the STLE, which is equal to the number of current variables in the STLE, is attained. The number of input gates of the MITEs is minimal amongst those MITE networks that satisfy the STLE and have the minimum number of MITEs. The synthesized MITE networks have a unique operating point and, in many cases, the network is guaranteed to be stable in a particular sense. This synthesis procedure exploits the relationship between MITE product-of-power-law (POPL) networks and linear diophantine equations which is explored in detail here.

In this paper, we briefly discuss a methodology for synthesizing analog systems from a high-level behavioral specification using a class of circuits called dynamic translinear circuits. We illustrate this method by synthesizing a Least-Mean-Square (LMS) adaptation algorithm used in an analog adaptive filter. The resulting systems can be simulated at various levels of abstraction during the design phase. As an example, we present simulation results from a four-tap analog adaptive filter simulated using Matlab and SPICE.

We explore homeostasis in a silicon integrate-and-fire neuron. The neuron adapts its firing rate over time periods on the order of seconds or minutes so that it returns to its spontaneous firing rate after a sustained perturbation. Homeostasis is implemented via two schemes. One scheme looks at the presynaptic activity and adapts the synaptic weight depending on the presynaptic spiking rate. The second scheme adapts the synaptic "threshold" depending on the neuron's activity. The threshold is lowered if the neuron's activity decreases over a long time and is increased for prolonged increase in postsynaptic activity. The presynaptic adaptation mechanism models the contrast adaptation responses observed in simple cortical cells. To obtain the long adaptation timescales we require, we used floating-gates. Otherwise, the capacitors we would have to use would be of such a size that we could not integrate them and so we could not incorporate such long-time adaptation mechanisms into a very large-scale integration (VLSI) network of neurons. The circuits for the adaptation mechanisms have been implemented in a 2-/spl mu/m double-poly CMOS process with a bipolar option. The results shown here are measured from a chip fabricated in this process.

In this paper, the author discusses an approach to the synthesis of dynamic translinear circuits built from multiple-input translation elements (MITEs). In this method, we realize separately the basic static nonlinearities and dynamic signal-processing functions that when cascaded together, form the system that one wishes to construct. The circuit is then simplified systematically through local transformations that do not alter the behavior of the system. The author illustrates the method by synthesizing a simple nonlinear dynamical system, an RMS-DC converter.

the author presents a new folded differential pair topology that is suitable for low-voltage applications. The new differential pair is made from floating-gate MOS (FGMOS) transistors and simultaneously provides a rail-to-rail common-mode input voltage range with a high rejection of the common-mode input voltage by keeping the sum of the two output currents fixed. Moreover, when biased in weak or moderate inversion, the allowable output voltage swing is also almost from rail-to-rail. The author discusses the operation of the circuit and some of the trade-offs involved in its design. He also shows experimental measurements from a version of the circuit, operating on a single 1.8 V power supply, that was breadboarded from transistors fabricated in a 1.2 /spl mu/m double-poly n-well CMOS process.

I discuss the importance of capacitor matching in the context of using charge stored on floating-gate MOS (FGMOS) transistors to compensate for transistor mismatch in analog circuits. I describe a simple technique that only involves static measurements for assessing the relative mismatch between capacitors. I also show experimental measurements of capacitor mismatch for small capacitors fabricated in 1.2-/spl mu/m and 0.35-/spl mu/m double-poly it n-well CMOS process that are commonly available.

In this work, we explore homeostasis in a silicon integrate-and-fire neu(cid:173) ron. The neuron adapts its firing rate over long time periods on the order of seconds or minutes so that it returns to its spontaneous firing rate after a lasting perturbation. Homeostasis is implemented via two schemes. One scheme looks at the presynaptic activity and adapts the synaptic weight depending on the presynaptic spiking rate. The second scheme adapts the synaptic "threshold" depending on the neuron's activity. The threshold is lowered if the neuron's activity decreases over a long time and is increased for prolonged increase in postsynaptic activity. Both these mechanisms for adaptation use floating-gate technology. The re(cid:173) sults shown here are measured from a chip fabricated in a 2-J.lm CMOS process.

We describe the design, fabrication, characterization, and modeling of an array of single transistor synapses. The single transistor synapses simultaneously perform long term weight storage, compute the product of the input and floating gate value, and update the weight value according to a hebbian or a backpropagation learning rule. The charge on the floating gate is decreased by hot electron injection with high selectivity for a particular synapse. The charge on the floating gate is increased by electron tunneling, which results in high selectivity between rows, but much lower selectivity between columns along a row. When the steady state source current is used as the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current.

We describe single-transistor silicon synapses that compute, learn, and provide non-volatile memory retention. The single transistor synapses simultaneously perform long term weight storage, com(cid:173) pute the product of the input and the weight value, and update the weight value according to a Hebbian or a backpropagation learning rule. Memory is accomplished via charge storage on polysilicon floating gates, providing long-term retention without refresh. The synapses efficiently use the physics of silicon to perform weight up(cid:173) dates; the weight value is increased using tunneling and the weight value decreases using hot electron injection. The small size and low power operation of single transistor synapses allows the devel(cid:173) opment of dense synaptic arrays. We describe the design, fabri(cid:173) cation, characterization, and modeling of an array of single tran(cid:173) sistor synapses. When the steady state source current is used as the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current. The synaptic array was fabricated in the standard 21'm double - poly, analog process available from MOSIS.

We present a silicon model of an axon which shows promise as a building block for pulse-based neural computations involving cor(cid:173) relations of pulses across both space and time. The circuit shares a number of features with its biological counterpart including an excitation threshold, a brief refractory period after pulse comple(cid:173) tion, pulse amplitude restoration, and pulse width restoration. We provide a simple explanation of circuit operation and present data from a chip fabricated in a standard 2Jlm CMOS process through the MOS Implementation Service (MOSIS). We emphasize the ne(cid:173) cessity of the restoration of the width of the pulse in time for stable propagation in axons.