Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from VLDB 2026 / reviewers in the wild / expert

Bruce E. Emerson

dblp:87/5044 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 61% Integrated circuit design · 30% Electronic design automation · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › image processing accelerator
hough transform processor		 0.011988
A Monolithic Hough Transform Processor Based on Restructurable VLSI · IEEE Trans. Pattern Anal. Mach. Intell. 1988
Hardware accelerators and domain-specific architectures
image processing accelerator		 0.011988
A Monolithic Hough Transform Processor Based on Restructurable VLSI · IEEE Trans. Pattern Anal. Mach. Intell. 1988
Integrated circuit design › VLSI design
wafer-scale integration		 0.011988
A Monolithic Hough Transform Processor Based on Restructurable VLSI · IEEE Trans. Pattern Anal. Mach. Intell. 1988
Electronic design automation
design automation tools		 0.011988
A Monolithic Hough Transform Processor Based on Restructurable VLSI · IEEE Trans. Pattern Anal. Mach. Intell. 1988

Methods — techniques the papers use, named apart from their topics

wafer-scale integration · 0.0hough transform · 0.0
YearPublicationVenuePosition
1988 A Monolithic Hough Transform Processor Based on Restructurable VLSI
abstract
The implementation of a Hough transform processor using a wafer-scale-integration technology, restructurable VLSI circuit is described. The Hough transform is typically used as a grouping operation in an image processing sequence. The transform discussed here groups pixels in order to extract linear features. This calculation is realized with a wafer-scale processor that allows a complete line extraction system to be integrated on a single PC board. Also discussed is the use of the CAD tools that allowed this processor to be realized without incurring silicon layout and processing overhead.>
F. Matthew Rhodes, Joseph J. Dituri, Glenn H. Chapman, Bruce E. Emerson, Antonio M. Soares, Jack I. Raffel
 IEEE Trans. Pattern Anal. Mach. Intell.4