We present an iterative equalization scheme that accounts for both inter-carrier interference (ICI) and inter-symbol interference (ISI) on multicarrier communication systems without a cyclic prefix (CP). We employ two equalizers based on the BCJR algorithm that process data in the two-dimensional (2D) time-frequency space; the equalizers exchange soft-bit information with each other and with a channel decoder. We generalize an existing iterative maximum likelihood equalizer (IMLE) to account for ICI-ISI and compare against it. We also use a 1D ICI-only BCJR equalizer with full CP as a baseline. We show that, in presence of moderate amounts of ICI-ISI, our equalizers improve bit error rate (BER) by exploiting Doppler and time diversity. In fact, our CP-free ICI-ISI equalizers achieve the same performance as the full CP ICI-only equalizer on some channels, which results in a data throughput gain. Furthermore, BERs as low as 10-6are achieved in high-spread channels that surpass the orthogonal time-frequency space (OTFS) crystallization condition for interference-free transmission. Even when perfect channel state information (CSI) is not available, our equalizers are more robust, outperforming the IMLE despite higher CSI estimation error variance.

We propose a three-track detection system for two dimensional magnetic recording (TDMR) in which a local area influence probabilistic (LAIP) detector works with a trellis-based Bahl-Cocke-Jelinek-Raviv (BCJR) detector to remove intersymbol interference (ISI) and intertrack interference (ITI) among coded data bits as well as media noise due to magnetic grain-bit interactions. Two minimum mean-squared error (MMSE) linear equalizers with different response targets are employed before the LAIP and BCJR detectors. The LAIP detector considers local grain-bit interactions and passes coded bit log-likelihood ratios (LLRs) to the channel decoder, whose output LLRs serve as a priori information to the BCJR detector, which is followed by a second channel decoding pass. Simulation results under 1-shot decoding on a grain-flipping-probability (GFP) media model show that the proposed LAIP/BCJR detection system achieves density gains of 10.16% for center-track detection and 3.13% for three-track detection compared to a standard BCJR/1D-PDNP. The proposed system's BCJR detector bit error rates (BERs) are lower than those of a recently proposed two-track BCJR/2D-PDNP system by factors of (0.55, 0.08) for tracks 1 and 2 respectively.

We present an extrinsic information transfer (EXIT) chart-based design technique for irregular repeat-accumulate (IRA) codes used in 2-D magnetic recording (TDMR) turbo-equalization systems. The channel model includes Voronoi magnetic grains, 2-D intersymbol interference (2D-ISI) and additive white Gaussian noise (AWGN). The receiver uses a 2D-ISI BCJR equalizer and an IRA decoder. For one outer equalizer-decoder iteration, we propose theory and simulation-based methods for computing EXIT curves. The simulation method calculates experimental EXIT curves for the check node decoder (CND) and the combination of the variable node decoder (VND) and an equalizer. The theoretical approach recursively calculates CND and VND Gaussian mixture model parameters in order to calculate EXIT curves. We then fit the VND and CND EXIT curves to find optimized variable node degree distributions. Simulation results show that the TDMR-optimized IRA codes achieve up to a 6.2% density increase in user bits/grain (U/G) compared with IRA codes designed for AWGN channels. The theory-based code designs achieve the same or better U/G as the simulation-based designs, but require 98% less design computation time. We also derive optimized IRA codes for iterative turbo-equalization; these codes can achieve simultaneous U/G gains and SNR savings compared with AWGN-optimized codes.

This paper considers turbo equalization for 2-D magnetic recording. Magnetic grains are modeled as Voronoi regions of randomly distributed nuclei. Bits read from the magnetic grain model flow into a 2-D intersymbol interference (2D-ISI) model including additive white Gaussian noise. At high bit densities, some bits are not written on any grain, and hence are effectively “overwritten” by surrounding bits. The proposed system iteratively exchanges log-likelihood ratios (LLRs) between a 2D-ISI equalizer based on the forward-backward algorithm and an irregular repeat-accumulate (IRA) decoder. To combat bit overwrites, the system employs a non-linear function to map 2D-ISI extrinsic output LLRs to IRA decoder input LLRs. To pass back LLRs from the IRA decoder to the 2D-ISI equalizer, we design a simple likelihood-ratio-based LLR estimator. Simulations of the proposed system that employ the perturbed-bit-centers grain model proposed in a 2010 IEEE Transactions on Magnetics paper show a 6.5% increase in user bits per grain (U/G) and a 16.4 dB signal-to-noise ratio (SNR) gain compared with the previous paper, without iterative turbo equalization. Utilizing the LLR estimator to do iterative detection results in SNR gains of up to 1.7 dB compared with non-iterative detection. The random Voronoi model employed in this paper appears to be more difficult to equalize than the grain model in the 2010 paper. The proposed system with random Voronoi model achieves 0.4422 U/G at SNR =11.6 dB, i.e., about 8.8 Tb/in2at (typically assumed future grain density) 20 Tgr/in2; this is almost ten times the density of current systems at 10 Tgr/in2.

The Network-on-Chip (NoC) paradigm is used as a scalable interconnection infrastructure for multi-core chips. To enhance the performance of conventional interconnect-based multi-core chips, on-chip wireless interconnect has emerged as a radically different technology. However, this emerging interconnect paradigm imposes significant challenges pertaining to reliable integration and design. In this paper, we focus on two types of mm-wave wireless NoC architectures. One is a hierarchical architecture with long-range wireless shortcuts and the other is a power-law connectivity based small-world network without any hierarchy. We demonstrate that though the hierarchical architecture offers more bandwidth with lower energy dissipation than the small-world-based counterpart, it has significantly more area overhead. Also, the power-law connectivity based small-world wireless NoC is more robust in presence of wireless link failures.

The Network-on-chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing methods of implementing a NoC with planar metal interconnects are deficient due to high latency and significant power consumption arising out of multihop links used in data exchange. To address these problems, we propose design of a hierarchical small-world wireless NoC architecture where the multihop wire interconnects are replaced with high-bandwidth and single-hop long-range wireless shortcuts operating in the millimeter (mm)-wave frequency range. The proposed mm-wave wireless NoC (mWNoC) outperforms the corresponding conventional wireline counterpart in terms of achievable bandwidth and is significantly more energy efficient. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously further enhance the performance, and provide an energy-efficient solution for design of communication infrastructures for multicore chips.

Traditional many-core designs based on the Network-on-Chip (NoC) paradigm suffer from high latency and power dissipation as the system size scales up due to their inherent multi-hop communication. NoC performance can be significantly enhanced by introducing long-range, low power, and high-bandwidth single-hop wireless links between far apart cores. This paper presents a design methodology and performance evaluation for a hierarchical small-world NoC with CMOS compatible on-chip millimeter (mm)-wave wireless long-range communication links. The proposed wireless NoC offers significantly higher bandwidth and lower energy dissipation compared to its conventional non-hierarchical wired counterpart in presence of both uniform and non-uniform traffic patterns. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously provide an energy efficient solution for design of many-core communication infrastructures.

Massive levels of integration are making modern multicore chips all pervasive in several domains. High performance, robustness, and energy-efficiency are crucial for the widespread adoption of such platforms. Networks-on-Chip (NoCs) have emerged as communication backbones to enable a high degree of integration in multicore Systems-on-Chip (SoCs). Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multihop links with high latency and power consumption. This limitation can be addressed by drawing inspiration from the evolution of natural complex networks, which offer great performance-cost trade-offs. Analogous with many natural complex systems, future multicore chips are expected to be hierarchical and heterogeneous in nature as well. In this article we undertake a detailed performance evaluation for hierarchical small-world NoC architectures where the long-range communications links are established through the millimeter-wave wireless communication channels. Through architecture-space exploration in conjunction with novel power-efficient on-chip wireless link design, we demonstrate that it is possible to improve performance of conventional NoC architectures significantly without incurring high area overhead.

Multicore platforms are emerging trends in the design of System-on-Chips (SoCs). Interconnect fabrics for these multicore SoCs play a crucial role in achieving the target performance. The Network-on-Chip (NoC) paradigm has been proposed as a promising solution for designing the interconnect fabric of multicore SoCs. But the performance requirements of NoC infrastructures in future technology nodes cannot be met by relying only on material innovation with traditional scaling. The continuing demand for low-power and high-speed interconnects with technology scaling necessitates looking beyond the conventional planar metal/dielectric-based interconnect infrastructures. Among different possible alternatives, the on-chip wireless communication network is envisioned as a revolutionary methodology, capable of bringing significant performance gains for multicore SoCs. Wireless NoCs (WiNoCs) can be designed by using miniaturized on-chip antennas as an enabling technology. In this paper, we present design methodologies and technology requirements for scalable WiNoC architectures and evaluate their performance. It is demonstrated that WiNoCs outperform their wired counterparts in terms of network throughput and latency, and that energy dissipation improves by orders of magnitude. The performance of the proposed WiNoC is evaluated in presence of various traffic patterns and also compared with other emerging alternative NoCs.

In a traditional Network-on-Chip (NoC), latency and power dissipation increase with system size due to its inherent multi-hop communications. The performance of NoC communication fabrics can be significantly enhanced by introducing long-range, low power, high bandwidth direct links between far apart cores. In this paper a design methodology for a scalable hierarchical NoC with on-chip millimeter (mm)-wave wireless links is proposed. The proposed wireless NoC offers significantly higher throughput and lower energy dissipation compared to its conventional multi-hop wired counterpart. It is also demonstrated that the proposed hierarchical NoC with long range wireless links shows significant performance gains in presence of various application-specific traffic and multicast scenarios.

We present a novel iterative soft decision feedback zig-zag algorithm for detection of binary images corrupted by two dimensional intersymbol interference and additive white Gaussian noise. The algorithm exchanges soft information between maximum-a-posteriori detectors employing different zigzag scan directions. Each detector exploits soft-decision feedback from the other zig-zag detectors. Simulation results for the 2 × 2 averaging mask channel show that, at low signal-to-noise ratios, the new algorithm gains about 1 dB over an iterative row column soft decision feedback algorithm and over a separable mask algorithm, two of the best previously published schemes. When the zig-zag algorithm is concatenated with the row-column algorithm, the concatenated system performs as well as or better than four of the best previously published algorithms, at both low and high signal-to-noise ratios, for a variety of 2 × 2 and 3 × 3 convolution masks; in several cases, the system performs within less than 0.1 dB of the maximum-likelihood performance bound.

Network-on-chip (NOC) is emerging as a revolutionary methodology to integrate numerous intellectual property blocks in a single die. It is the packet switching-based communications backbone that interconnects the components on multicore system-on-chip (SoC). A major challenge that NOC design is expected to face is related to the intrinsic unreliability of the interconnect infrastructure under technology limitations. By incorporating error control coding schemes along the interconnects, NOC architectures are able to provide correct functionality in the presence of different sources of transient noise and yet have lower overall energy dissipation. In this paper, designs of novel joint crosstalk avoidance and triple-error-correction/quadruple-error-detection codes are proposed, and their performance is evaluated in different NOC fabrics. It is demonstrated that the proposed codes outperform other existing coding schemes in making NOC fabrics reliable and energy efficient, with lower latency.

We consider BCJR-like soft-input soft-output (SISO) iterative detection algorithms for 1D and 2D binary-input ISI channels with AWGN. The complexity of BCJR algorithms grows exponentially with the size of the ISI mask and is an important concern with their implementation. We consider new techniques to reduce the complexity of BCJR algorithms by decreasing the effective number of states in the trellis. The proposed state reduction technique does particularly well for mixed phase sequence ISI masks, which have higher weights for the center taps and lower weights for the peripheral taps. Other complexity reduction techniques proposed in the literature perform poorly for such masks. Moreover, the complexity of the proposed state reduction technique is comparable to other reduced complexity techniques reported in the literature. Experimental results are provided to demonstrate the advantages of the proposed state reduction technique.

With the well-known trend of CMOS scaling as per Moore’s Law, traditional on-chip interconnect systems are reaching the point of having a very limited ability to meet the performance needs and specifications of Systems-on-Chip (SoCs). The conventional two-dimensional (2D) copper-based IC has inherent limitations due to the geometrical constraints of the planar structure. Innovative interconnect paradigms based on optical technologies, RF/wireless, carbon nanotubes, or 3D integration are promising alternatives that may indeed overcome the challenges encountered. In this paper we present an overview of different emerging non-traditional approaches to achieve massive degree of integration in a single chip. The advantages and underlying challenges of each method are highlighted.

We present a novel iterative row-column soft decision feedback algorithm (IRCSDFA) for detection of binary images corrupted by 2-D intersymbol interference and additive white Gaussian noise. The algorithm exchanges weighted soft information between row and column maximuma posteriori(MAP) detectors. Each MAP detector exploits soft-decision feedback from previously processed rows or columns. The new algorithm gains about 0.3 dB over the previously best published results for the 2times2 averaging mask. For a non-separable 3times3 mask, the IRCSDFA gains 0.8 dB over a previous soft-input/soft-output iterative algorithm which decomposes the 2-D convolution into 1-D row and column operations.

We design 1-b/symbol/Hz parallel concatenated turbo-coded modulation (PCTCM) for the additive white Gaussian noise (AWGN) channel with Tikhonov phase error. Constituent recursive convolutional codes are optimized so that the turbo codes have low error floors and low convergence thresholds. The pairwise error probability based on the maximum-likelihood decoding metric is used to select codes with low error floors. We also present a Gaussian approximation method that accurately predicts convergence thresholds for PCTCM codes on the AWGN/Tikhonov channel. Simulation results show that the selected codes perform within 0.6 dB of constellation constrained capacity, and have no detectable error floor down to bit-error rates of 10/sup -6/.

A video transmission system is presented based on the 3D SPIHT (set partitioning in hierarchical trees) algorithm for video compression and turbo codes for channel error protection. The channel considered is a binary symmetric channel with packet erasures, used for modeling the concatenation of a congested wired link followed by a noisy wireless hop. Unequal error protection with turbo codes is used to provide strong channel protection, with rate allocation performed by a Viterbi-based algorithm. The received video quality degrades gracefully in the presence of channel errors.

A method of combined source and channel coding is described that provides robustness to errors from a binary symmetric channel and uses the JPEG2000 (JP2) image compression standard. The source code rate and channel code rate are jointly optimized to produce a stream of fixed-size channel packets, such that the rate allocation complexity grows O(N/sup 2/) with the number of transmitted packets, N. Punctured turbo codes are used for channel coding, providing strong error protection. The rate allocation scheme presented obtains all necessary information from the JP2 encoder, and does not require image decompression.

This paper presents numerical capacity curves for two discrete complex channels: (1) a slow-fading Rayleigh channel with discrete carrier tracking by a phase-locked loop (PLL), where the PLL SNR is proportional to the fading amplitude squared, and (2) a fast-fading Rician channel with carrier phase estimation for the line-of-sight path only. Both channel models assume independent fading of successively received symbols. Capacity calculations are performed for equiprobable signaling with 8-ary and 16-ary amplitude-modulated phase-shift-keyed (AM-PSK) constellations. On the Rayleigh channel, the AM-PSK constellations give gains between 2 and 9 dB over PSK, at SNRs between 5 and 40 dB. For the Rician channel, AM-PSK gives a capacity gain over PSK of up to 0.75 bit at high SNR.

This work describes a method for providing robustness to errors from a binary symmetric channel for the JPEG2000 (J2K) image compression standard. It does so while maintaining full J2K compliance. The source rate and channel rate are jointly optimized by using a Viterbi Algorithm (VA) on a stream of fixed-size channel packets, such that the rate allocation complexity grows O(N/sup 2/) with the number of transmitted packets. Punctured turbo codes are used for the channel coding, providing stronger error protection than previously available codes. The rate allocation scheme presented obtains all necessary information from the J2K encoder, and does not require image decompression.

This paper derives truncated union bounds on the a priori index crossover probabilities p(j|i) that result when an n-bit data index i is convolutionally encoded, transmitted over a noisy channel, and decoded with the Viterbi algorithm, giving received index j. The bounds are derived with a modified transfer function technique, using n-stage state transition matrices with symbolic labels. The technique is easily automated with commercial symbolic algebra packages. Bounds are obtained for convolutional and trellis-coded modulation (TCM) codes, over binary symmetric and additive white Gaussian noise (AWGN) channels. A joint source channel coding example demonstrates that the bounds on p(j|i) developed in this paper can give a 13-dB accuracy improvement in end-to-end signal-to-noise ratio (SNR) predictions, when compared to predictions based on bounds on the delivered bit error probability P/sub b/.

We present here design techniques for trellis-coded vector quantizers with symmetric codebooks that facilitate low-complexity quantization as well as partitioning into equiprobable sets for trellis coding. The quantization performance of this coder on the independently identically distributed (i.i.d.) Laplacian source matches the performance of trellis-based scalar-vector quantization (TB-SVQ), but requires less computational complexity.

Trellis coded vector quantization is known to offer a good rate-distortion performance, but at a considerable (and sometimes prohibitive) complexity cost. We present design techniques for vector quantizers with highly symmetric codebooks that facilitate low complexity quantization as well as partitioning into equiprobable sets for trellis coding. The quantization performance of this coder on the Laplacian source matches the performance of trellis based scalar-vector quantization, the best fixed-wordlength quantizer thus far reported, but requires less computational complexity. Furthermore, this coder is well-suited for use in joint source/channel coding systems where the codeword locations and labeling are chosen to minimize the effects of channel errors.

Lattice vector quantization schemes offer high coding efficiency without the burden associated with generating and searching a codebook. The distortion associated with a given lattice is often expressed in terms of the G number, which is a measure of the mean square error per dimension generated by quantization of a uniform source. Subband image coefficients, however, are best modeled by a generalized Gaussian, leading to distortion characteristics that are quite different from those encountered for uniform, Laplacian, or Gaussian sources. We present here the distortion associated with Z, E/sub 8/, and Leech lattice quantization for coding of generalized Gaussian sources, and show that for low bit rates the Z lattice offers both the best performance and the lowest implementational complexity.

The design of a low complexity joint source channel codec for images using trellis coded quantization and convolutional codes is studied. It is shown that a low complexity joint source channel codec offering high robustness is enabled by using the same Ungerboeck trellis code to do both quantization and convolutional coding. Simulation results are presented for joint source channel coding of Gaussian sources over the additive white Gaussian noise channel (AWGN) under the restriction of BPSK modulation; coding of image subband coefficients is also performed. The results compare favorably with those previously reported for systems employing unified trellis source coding and convolutional channel coding, and for pseudo-Gray coded systems. The simulation results also show that there is an optimal allocation of transmission bandwidth between the source and channel codes.

In lattice vector quantization, the distortion associated with a given lattice is often expressed in terms of the G number, which is a measure of the mean square error per dimension generated by quantization of a uniform source. Subband image coefficients, however, are best modeled by a generalized Gaussian distribution, leading to distortion characteristics that are quite different from those encountered for uniform, Laplacian, or Gaussian sources. We have calculated the distortion associated with Z, E/sub 8/, and Leech (1967) lattice quantization for coding of generalized Gaussian sources and show that for low bit rates, the Z lattice offers both the best performance and the lowest implementational complexity.>

Choice of filter bank in wavelet compression is a critical issue that affects image quality as well as system design. Although regularity is sometimes used in filter evaluation, its success at predicting compression performance is only partial. A more reliable evaluation can be obtained by considering an L-level synthesis/analysis system as a single-input, single-output, linear shift-variant system with a response that varies according to the input location module (2(L),2(L)). By characterizing a filter bank according to its impulse response and step response in addition to regularity, we obtain reliable and relevant (for image coding) filter evaluation metrics. Using this approach, we have evaluated all possible reasonably short (less than 36 taps in the synthesis/analysis pair) minimum-order biorthogonal wavelet filter banks. Of this group of over 4300 candidate filter banks, we have selected and present here the filters best suited to image compression. While some of these filters have been published previously, others are new and have properties that make them attractive in system design.

Choice of filter bank in wavelet compression is a critical issue that affects image quality as well as system design. Although regularity is sometimes used in filter evaluation, its success at predicting compression performance is only partial. A more reliable evaluation can be obtained by considering an L-level synthesis/analysis system as a single-input, single-output, linear shift-variant system with a response that varies according to the input location modulo (2/sup L/, 2/sup L/). By characterizing a filter bank according to its impulse response and step response in addition to regularity, the authors obtain reliable and relevant (for image coding) filter evaluation metrics. Using this approach, they have evaluated all possible reasonably short (less than 34 taps in the synthesis/analysis pair) minimum order biorthogonal wavelet filter banks. Of this group of over 4300 candidate filter banks, they have selected and presented the filters best suited to image compression. While some of these filters have been published previously, others are new and have properties that make them attractive in system design.>

Wireless video transmission over a dynamic network requires adaptation to changes in bandwidth, network traffic, and channel characteristics. New computing hardware and algorithms are needed that enable low-power, flexible, adaptive, and robust video communication in hostile environments with no access to an installed communications infrastructure. The coding algorithms we are developing are based on subband decomposition using integer-coefficient filters, and adaptively deliver video at rates between 60 kbits/sec and 600 kbits/sec in accordance with the available bandwidth. Robustness in the variable length coder is obtained by using low-overhead Reed-Solomon block codes, by performing intra-frame coding only, and by using end-of-frame and end-of-subband symbols to maintain both inter- and intra-frame synchronization.>