By focusing on chip-wide slices of the global routing grid, making a few mild geometric assumptions about layer use, and suitably abstracting pin details, we derive an efficient integer linear programming formulation for track/layer assignment. The key technical insight is to model all constraints both geometric and crosstalk - as cliques in an appropriate conflict graph; these cliques can be extracted quickly from the interval structure of wires in a slice. We develop a "strong" linear relaxation of this problem that almost always yields the integral optimum; this solution gives us directly the maximum number of wires that can be packed legally without crosstalk risk. Experiments on synthetic netlists that match statistics of wire layouts from industrial 0.25-/spl mu/m designs demonstrate that we can pack 100-1000 wires optimally or, at worst, a very few overflows in seconds.

By focusing on chip-wide slices of the global routing grid, making a few mild geometric assumptions about layer use, and suitably abstracting pin details, we derive an extremely effcient integer linear programming (ILP)formulationfor track/layer assignment.They key technical insight is to model all constraints-both geometric and crosstalk--as cliques in an appropriate conflict graph; these cliques can be extracted quickly from the interval structure of wires in a slice.We develop a "strong" linear relanation of this problem that almost always yields the integral optimum; this solution gives us directly the maximum number of wires that can pack legally without crosstalk risk.Experiments on synthetic netlists that match statistics of wire layouts from industrial 0.25um designs demonstrate that we can pack 100 -1000 wires optimally, or with at worst a very few over$ows, in seconch.

Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay (first moment of the impulse response) expression, to moment matching methods which create reduced order transimpedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer function delays are impractical for use as early-phase design metrics or as design optimization cost functions. This paper describes an approach for fitting moments of the impulse response to probability density functions so that delays can be estimated from probability tables. For RC trees it is demonstrated that the incomplete gamma function provides a provably stable approximation. The step response delay is obtained from a one-dimensional table lookup.

The wire sizing problem under inequality Elmore delay constraints is known to be posynomial, hence convex under an exponential variable transformation. Due to their efficiency and ease of implementation, one-wire-at-a-time downhill improvement heuristics are often applied to solve such problems. Unfortunately, when there are complex boundary constraints, the solutions from such heuristics can be far away from the global minimum. There are formal methods for solving convex programs, but they are too costly in terms of runtime for some applications. Some optimization techniques can be quite efficient but they solve less desirable formulations, such as minimum weighted sum of area and critical path delays. This paper proposes an efficient wire-sizing algorithm (EWA) that is able to trade solution accuracy for time efficiency while providing an upper bound on the distance from the optimal solution. EWA solves the practical problem of minimizing the total wiring area or the capacitance of an interconnect RC tree subject to hard constraints on the Elmore delay. The implementation is simple and efficiency is comparable to the available heuristics. No restrictions are placed on the circuit or wire widths. Furthermore, it is shown that the optimal wire width assignment for a minimum wiring area objective satisfies all the delay constraints as equalities when minimum wire width constraints are not active. It follows that EWA can be applied for problems with equality delay constraints such as clock trees. Moreover, this and other properties are general enough to permit extensions to higher order delay models and can be used to enhance other optimization methods.

The wire sizing problem under inequality Elmore delay constraints is known to be posynomial, hence convex under an exponential variable-transformation. There are formal methods for solving convex programs. In practice heuristics are often applied because they provide good approximations while offering simpler implementation and better efficiency. There are methods for solving related problems, which are comparable to heuristics from efficiency point of view, but they solve a less desirable formulation in terms of the objective function and constraints. In this paper the EWA algorithm is described. It solves the problem of minimizing the wiring area or capacitance of an interconnect tree subject to constraints on the Elmore delay. EWA is simple to implement and its efficiency is comparable to the available heuristics. No restrictions are placed on the circuit or wire widths, e.g., non-monotone wire widths assignment solutions are feasible. We prove that the optimal wire width assignment for a minimum wiring area objective satisfies all the delay constraint as equalities, when minimum wire width constraints are relaxed. It follows that EWA can be applied also for problems with equality delay constraints such as clock trees. This and other described properties are general enough to permit extensions to higher order delay models in the future.