Vertical Fixed Pattern Noise (VFPN) is a significant issue in CMOS image sensors that employ column-parallel Analog-to-Digital Converters (ADCs). Variations in column response due to Process, Voltage, Temperature (PVT) characteristics and differential non-linearity (DNL) in ADCs contribute to VFPN, which impacts the perceptibility of noise in images. This paper proposes two primary methods for reducing VFPN: analog offset dithering to mitigate quantization noise and dynamic counter clock adjustment to compensate for DNL variation. Simulation results using sensor measurement data demonstrate that these techniques significantly reduce VFPN by randomizing quantization noise and averaging DNL-induced variations across columns. The proposed methods achieve an improvement in VFPN uniformity of over 70%, effectively enhancing image quality.

In this work, we propose the first bit-level sparsity-aware SAR ADC with direct hybrid encoding for signed expressions (HESE) for AIoT applications. ADCs are typically a bottleneck in reducing the energy consumption of analog neural networks (ANNs). For a pre-trained Convolutional Neural Network (CNN) inference, a HESE SAR for an ANN can reduce the number of non-zero signed digit terms to be output, and thus enables a reduction in energy along with the term quantization (TQ). The proposed SAR ADC directly produces the HESE signed-digit representation (SDR) using two thresholds per cycle for 2-bit look-ahead (LA). A prototype in 65nm shows that the HESE SAR provides sparsity encoding with a Walden FoM of 15.2fJ/conv.-step at 45MS/s. The core area is 0.072mm2.

This work details the non-invasive evaluation of a carotid arterial blood pressure (ABP) waveform during the Valsalva maneuver. Unfocused and wide acoustic beams are insonated on the carotid artery to achieve motion-tolerant measurements with a simple two-element ultrasound scanner. Arterial flow and distension waveforms are reliably estimated from spectral Doppler and M-mode ultrasound images whose qualities are consistently maintained in different phases of the maneuver despite possible displacements of the artery. A local pulse wave velocity is estimated using a flow-area method, and it is then combined with the distension waveform to produce the ABP waveform. Human subject validation on seven healthy subjects shows that the bias in pulse pressure estimates across subjects is 0.47 ± 13.1 mmHg. The average root mean square deviations of the ultrasonically measured waveform across subjects is 10.1 ± 2.43 mmHg, excluding the strain phase of the Valsalva maneuver, and 17.7 ± 6.30 mmHg in all phases. The mean correlation coefficient between the ultrasonically measured and reference waveform is calculated to be 0.92 ± 0.04 across subjects. Detailed morphological features and their changes across different phases are observed as reported. This uninterrupted central ABP waveform monitoring under hemodynamics changes supports the idea of a novel stress test to evaluate the health and dynamics of the cardiovascular system at a spot check in clinical settings.

Automatic transistor sizing is a challenging problem in circuit design due to the large design space, complex performance tradeoffs, and fast technology advancements. Although there have been plenty of work on transistor sizing targeting on one circuit, limited research has been done on transferring the knowledge from one circuit to another to reduce the re-design overhead. In this paper, we present GCN-RL Circuit Designer, leveraging reinforcement learning (RL) to transfer the knowledge between different technology nodes and topologies. Moreover, inspired by the simple fact that circuit is a graph, we learn on the circuit topology representation with graph convolutional neural networks (GCN). The GCN-RL agent extracts features of the topology graph whose vertices are transistors, edges are wires. Our learning-based optimization consistently achieves the highest Figures of Merit (FoM) on four different circuits compared with conventional black box optimization methods (Bayesian Optimization, Evolutionary Algorithms), random search and human expert designs. Experiments on transfer learning between five technology nodes and two circuit topologies demonstrate that RL with transfer learning can achieve much higher FoMs than methods without knowledge transfer. Our transferable optimization method makes transistor sizing and design porting more effective and efficient.

Least Significant Bit-first (LSB-first) algorithm is suitable for low-activity signals as it reduces DAC activity and the number of bit-cycles required per conversion. However, certain code transitions degrade performance by requiring large switching energy and number of bit-cycles even when the code change over previous code is small. This paper addresses it by a new algorithm called Recode then LSB-first (RLSB-first) that reduces the switching energy required for all cases of small code change across the full range of possible previous sample codes. The energy reduction is achieved while maintaining a low number of bit-cycles per conversion.

This paper presents the design of a 6th-order continuous-time bandpass delta-sigma modulator that achieves in simulation over 75 dB SNDR across 25-MHz bandwidth with a center frequency at 250 MHz. On the architectural level, the SNR-limiting factor is identified and analyzed. A combined feedback-and-feedforward topology is employed that both reduces the number of feedback DACs and effectively suppresses the thermal noise from the 1stresonator by over 7 dB. On the transistor level, this paper focuses the discussion on the loop filter. The effect of op amp non-ideality is studied. A 5th-order multistage feedforward op amp is proposed to enhance loop filter linearity. Simulated in a 65 nm CMOS process, this design consumes 156 mW from a 1.2 V supply at a clock frequency of 1 GHz, predicting a state-of-the-art Walden figure-of-merit (FoM) of 0.597 pJ/step.

A technique for sampling clock skew correction by adjusting the delay in the input signal to each channel in a time-interleaved (TI) ADC is proposed. A proof-of-concept TI ADC employing this technique was implemented in a 65 nm CMOS process. The four-way TI ADC operates at an effective sampling rate of 150 MS/s, and achieves 60.2 dB and 58.2 dB SNDR for an input signal frequency of 2.1 MHz and 74.1 MHz, respectively. The ADC consumes 12.4 mW from a 1.2 V supply and occupies an area of 0.9 mm2.

This paper presents the design of a 4th-order multi-stage feedforward operational amplifier (op amp) for applications in continuous-time bandpass delta-sigma modulators. On the system-level, a design procedure is proposed to determine the transconductance of each stage. On the transistor-level, current-reusing is emphasized to achieve power efficiency. Simulated in a 65 nm CMOS process, the op amp achieves over 40 dB gain up to 500 MHz and over 10 dB gain up to 2 GHz with 10 mW powe consumption.

In this paper, we discuss and analyze the effectiveness of redundancy (also known as digital error correction) and its relationship with DAC settling time, comparator delay, digital logic delay and sampling rate in successive-approximation-register (SAR) ADCs. Behavioral models of SAR ADCs are developed that are four orders of magnitude faster than simulations done in FastSPICE, to predict ADC time progression and to quickly identify the maximum sampling rate that can be used in both redundant and non-redundant cases. We show that redundancy does not always improve sampling rate; instead, the maximum sampling rate depends on the relative magnitudes of different ADC delay components. SPICE simulation in a 65nm CMOS process verifies our behavioral simulation results.

This work introduces a simple, background offset cancellation scheme for zero-crossing based circuits (ZCBC). The ZCBC architecture has been proposed as an alternative to op-amp based analog to digital converts (ADC) because it does not suffer from the gain, stability, and settling time trade off. However, offset remains as a challenge. This work demonstrates an input offset cancellation scheme that employs a replica circuit to measure and then subtract the offset. The cancellation method has been applied to annm.

Since the first demonstration of a comparator-based switched-capacitor circuit, analog-to-digital (A/D) converters based on virtual ground detection have made steady and significant progress. Comparators have been replaced by zero-crossing detectors, leading to the development of zero-crossing based circuits for faster speed and lower power. All facets of performance including the sampling rate, effective number of bits, noise floor, and figure-of-merit have improved substantially. This paper focuses on recent implementations of zero-crossing based A/D converters and discusses the technical issues unique to these A/D converters as well as solutions that have been developed to improve their performance and practicality. A series of prototype designs whose performance ranges from 8 bit, 200 MS/s to 12 bit, 50 MS/s are described. The ultimate low power potentials of these A/D converters are compared with various different types of complementary metal-oxide-semiconductor A/D converters from a fundamental thermal noise standpoint.

Challenges in analog-to-digital (A/D) conversion for future scaled complementary metal-oxide-semiconductor (CMOS) technologies are investigated. The analysis of a figure of merit (FOM) that accounts for energy per conversion step indicates that op-amps are one of the most significant performance bottlenecks. New mixed-signal circuit architectures, which are more suitable for A/D conversion in scaled CMOS technologies and are more energy efficient than traditional architectures, are described. These circuits sense the crossing of virtual ground with comparators or zero-crossing detectors instead of forcing the virtual ground with op-amps. The FOM derivations for the comparator and zero-crossing based circuits indicate potentially a large improvement over traditional op-amp based circuits. The designs and experimental results of analog-to-digital converters based on a prototype comparator and zero-crossing are discussed in detail.

This work investigates the analysis of transient noise in non steady-state systems such as comparator-based switched-capacitor circuits. It expands the impulse sensitivity method previously applied to oscillator noise analysis to general linear time varying systems. The method described here uses simulation techniques to obtain the noise transfer function. This provides a useful tool for circuit design because it allows for the precision and ease of simulation without sacrificing the intuition of hand calculations.