Demo Data from VLDB 2026 / reviewers in the wild / expert
Shaori Guo
dblp:87/5775
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 2001
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-authorArtificial intelligence and machine learning · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 56% Reconfigurable computing and FPGAs · 44% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures
edge detection |
0.0 | 1 | 1994 | Developing Parallel Architectures for Range and Image Sensors · ICRA 1994 |
Reconfigurable computing and FPGAs › FPGA-based signal processing
FPGA-based image processing |
0.0 | 1 | 1994 | Developing Parallel Architectures for Range and Image Sensors · ICRA 1994 |
Hardware accelerators and domain-specific architectures › systolic array
systolic array implementation |
0.0 | 1 | 1994 | Developing Parallel Architectures for Range and Image Sensors · ICRA 1994 |
Methods — techniques the papers use, named apart from their topics
systolic architecture · 0.0parametrized edge detector · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2001 | An integrated system for developing regular array designs
Shaori Guo, Wayne Luk |
J. Syst. Archit. | 1 |
| 1994 | Developing Parallel Architectures for Range and Image SensorsabstractWe describe a cost-effective method for developing parallel architectures which increase the performance of range and image sensors. A parametrised edge detector and its systolic implementation using field-programmable gate arrays (FPGAs) are presented. Experiments and analyses indicate that our circuits can satisfy the performance requirements, and some of the designs out-perform the software equivalent on a 486-based PC by nearly two orders of magnitude.> Shaori Guo, Wayne Luk, Penny Probert Smith |
ICRA | 1 |