Demo Data from VLDB 2026 / reviewers in the wild / expert
Michael Harder
dblp:87/5932
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2005
0000-0002-5557-0946ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Software testing · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Software testing › test generation
test suite generation |
0.0 | 1 | 2003 | Improving Test Suites via Operational Abstraction · ICSE 2003 |
Software testing › regression testing
test suite reduction |
0.0 | 1 | 2003 | Improving Test Suites via Operational Abstraction · ICSE 2003 |
Software testing › test coverage
code coverage |
0.0 | 1 | 2003 | Improving Test Suites via Operational Abstraction · ICSE 2003 |
Methods — techniques the papers use, named apart from their topics
operational difference technique · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2005 | An Esterel processor with full preemption support and its worst case reaction time analysisabstractThe concurrent synchronous language Esterel allows programmers to treat reactive systems in an abstract, concise manner. An Esterel program is typically first translated into other, non-synchronous high-level languages, such as VHDL or C, and then compiled further into hardware or software. Another approach that has been proposed recently is the direct execution of Esterel-like instructions with a customized processor, which promises the flexibility of a software solution with an efficiency close to a hardware implementation. However, the instruction sets and implementations of the processor architectures proposed so far still have some limitations regarding their completeness, efficiency, and adherence to the original Esterel semantics. This paper presents a novel reactive processor architecture, the Kiel Esterel Processor, which addresses these shortcomings. In particular, it provides a complete, semantically accurate implementation of the Esterel preemption primitives, most of which can be expressed directly with a single machine instruction.One advantage of the reactive processors--in addition to their high execution speed compared to traditional software implementations--is that control-flow is preserved while compiling Esterel into machine code, and that the execution platform has a very predictable timing behavior. This paper presents a precise and very efficient Worst Case Reaction Time (WCRT) analysis, which is geared towards the Kiel Esterel Processor, but which could be adapted to other reactive processors as well. Xin Li 0020, Jan Lukoschus, Marian Boldt, Michael Harder, Reinhard von Hanxleden |
CASES | 4 |
| 2003 | Improving Test Suites via Operational AbstractionabstractThis paper presents the operational difference technique for generating, augmenting, and minimizing test suites. The technique is analogous to structural code coverage techniques, but it operates in the semantic domain of program properties rather than the syntactic domain of program text. The operational difference technique automatically selects test cases; it assumes only the existence of a source of test cases. The technique dynamically generates operational abstractions (which describe observed behavior and are syntactically identical to formal specifications)from test suite executions. Test suites can be generated by adding cases until the operational abstraction stops changing. The resulting test suites are as small, and detect as many faults, as suites with 100% branch coverage, and are better at detecting certain common faults. This paper also presents the area and stacking techniques for comparing test suite generation strategies; these techniques avoid bias due to test suite size. Michael Harder, Jeff Mellen, Michael D. Ernst |
ICSE | 1 |