With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.

A built-in self-repair (BISR) scheme for random access memories (RAMs) with 2-D redundancy has a built-in redundancy analyzer (BIRA) for allocating the redundancy. The BIRA typically has a cache-like element called local bitmap for storing the fault information temporary. In this paper, a high-repair-efficiency BISR (HRE-BISR) scheme for RAMs is proposed. The HRE-BISR reuses the local bitmap to serve as spare bits such that it can repair more faults. In addition, a row/column/bit redundancy analysis (RCB-RA) algorithm for a RAM with spare rows, spare columns, and spare bits is presented. Simulation results show that the proposed HRE-BISR scheme can provide higher repair rate (RR) than a typical BISR scheme without reusing the local bitmap as spare bits. Only about 0.44% additional hardware overhead is needed to modify the local bitmap as spare bits. In addition, the HRE-BISR scheme using 3 × 3-bit local bitmap for RA only incurs about 0.08-ns delay penalty for a 512 × 16 × 32-bit RAM with one spare row and one spare column. However, the HRE-BIRA scheme with RCB-RA algorithm can provide 0.48%-11.95% increment of RR for different fault distributions.

Three-dimensional (3-D) integration using through-silicon-via (TSV) is an emerging technology for integrated circuit (IC) design. It has been used in DRAM die stacking extensively. However, yield remains a key issue for volume production of 3-D RAMs. In this paper, we present a point-to-point interconnection structure derived from bus and propose a fault tolerance interface scheme for TSVs and micro bumps to enhance their manufacturing yield in the 3-D RAMs. The interconnection structure is inherently redundant and thus can replace defective TSVs or micro bumps without using repair circuits. Global and local reconfiguration approaches are proposed which benefit distinct situations of the 3-D RAM. Analyses show that the proposed intra-channel reconfigurable interconnection scheme can improve the yield of the 3-D RAM effectively. Compared to the previous solution using an inter-channel reconfigurable interconnection scheme, the yield improvement can be as large as 23% which is very significant.

This paper proposes a built-in self-test (BIST) scheme with syndrome-compression ability for random access memories (RAMs) with static (SF) and dynamic faults (DFs). A March-element-based (MEB) compression scheme is proposed to reduce the volume of diagnostic data. The MEB compression scheme can efficiently compress the diagnostic data of a RAM tested by a March test for detecting SFs and DFs. Simulation results show that the compression ratio (the ratio of the number bits of the compressed diagnostic data to that of the original diagnostic data) is about 50.79% for an 8K×16-bit memory. The area overhead of the BIST with the MEB compressor is about 2.73% for an 8K×16-bit RAM using TSMC 0.18 um cell library.

NAND flash memory is the most popular nonvolatile memory. Due to the specific mechanism of functional operations, flash memories are prone to disturbance faults. Furthermore, different NAND flash memories might have some differences on the array organizations and the supported functional operations. For example, some NAND flash memories can support the random program operation, but some cannot, some NAND flash memories with single-page word lines and some with multiple-page word lines. The differences on the array organizations and the functional operations result in the heavy influence on the testing of disturbance faults. In this paper, therefore, we analyze the disturbance faults for NAND flash memories with different array organizations and functional operations. Also, test algorithms for covering the disturbance faults in various types of NAND flash memories are developed.

A modern system-on-chip (SOC) may become one of the dies of a three-dimensional (3D) IC using through-silicon via (TSV). Built-in self-repair (BISR) techniques have been widely used to improve the yield of RAMs in a SOC. This paper proposes a memory BISR allocation scheme to allocate shared BISR circuits for RAMs in a SOC die such that the test and repair time and the area of BISR circuits are minimized. To minimize the test and repair time of RAMs in the pre-bond and post-bond test phases, a test scheduling engine is used to determine the pre-bond and post-bond test sequences of RAMs under the corresponding test power constraints. Then, a BISR-circuit minimization algorithm is proposed to reduce the number of required shared BISR circuits for the RAMs under the constraints of pre-bond and post-bond test sequences and distance between the BISR circuit and served RAMs. Simulation results show that in comparison with a dedicated BISR scheme (i.e., each RAM has a self-contained BISR circuit), 35% area reduction can be achieved by the shared BISR scheme planned by the proposed allocation technique under lmm distance constraint, and 500mW and 600mW pre-bond and post-bond test power constraints, respectively.

Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-correcting code (ECC) and redundancy (HEAR) technique to reduce the refresh power of DRAMs in standby mode. The HEAR circuit consists of a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to raise the error correction capability and minimize the adverse effects caused by the ECC technique such that the refresh period can be effectively prolonged and considerable refresh power reduction can be achieved. Analysis results show that the proposed HEAR scheme can achieve 40~70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63 % and 53 % of that of the ECC-only, respectively.

Summary form only given. Due to the specific mechanism of functional operations, flash memories are prone to disturbance faults. Furthermore, different NAND flash memories might have some differences on the array organizations and the supported functional operations. In this paper, therefore, test algorithms for covering the disturbance faults in various types of NAND flash memories are developed.

Built-in self-repair (BISR) techniques are widely used to enhance the yield of random access memories (RAMs) in a system-on-chip (SoC) which typically consists of hundreds of RAMs. Hence, many BISR circuits may be needed in a such SoC. Effective techniques for planning these BISR circuits thus are imperative. In this paper, we propose a memory BISR planning (MBiP) framework for the RAMs in SoCs. The MBiP framework consists of a memory grouping algorithm for selecting RAMs which can share a BISR circuit. Then, a test scheduling algorithm is used to determine the test sequence of RAMs in a SoC under the constraint of test power. Finally, a BISR scheme allocation algorithm is proposed to allocate different BISR schemes for the RAMs under the constraints of the results of memory grouping and test scheduling. Simulation results show that the proposed MBiP can effectively plan the BISR schemes for the RAMs in a SoC. For example, about 22% area reduction can be achieved by the BISR schemes planned by the proposed MBiP framework for 50 RAMs under 1.5 mm distance constraint and 350 mW test power constraint in comparison with a dedicated BISR scheme (i.e., each RAM has a self-contained BISR circuit).

Built-in self-repair (BISR) techniques are widely used to enhance the yield of memories in a system-on-chip (SOC). A SOC typically consists of hundreds of memories. Cost-efficient BISR schemes for repairing those memories thus are imperative. In this paper, we propose a memory BISR automatic generation (MBAG) framework for designing memory BISR circuits in a SOC. The MBAG framework consists of a test scheduling engine and a memory grouping engine for the minimization of test time and area cost of the BISR circuits. The test scheduling algorithm has been presented in our previous work [1]. In this paper, therefore, we focus on the introduction of the grouping algorithm determining the memories which can share a BISR circuit under the constraints of distance and scheduling results. Simulation results show that the proposed MBAG can generate reconfigurable BISR circuits for 20 memories such that 50% area reduction is achieved in comparison with a dedicated BISR scheme if the distance constraint is 3mm and the test power constraint is 80mW.

This paper proposes a simple method for enhancing the reliability of static random access memories (SRAMs) with hard-to-detect resistive-open defects. The method prevents a SRAM from executing successive multiple read operations on the same position, such that the hard-to-detect defects cannot manifest as functional faults. This can prolong the lifetime of the SRAM with latent hard-to-detect defects. Experimental results show that the proposed reliability-enhancement circuit (REC) can effectively improve the reliability of the SRAMs without incurring delay penalty and with 0.07% additional area cost for an 8192 × 64-bit SRAM. By integrating the REC with the SRAM, a BISR scheme is proposed to boost 6%-10% increment of repair rate compared with the BISR without the REC. Also, the area cost of the BISR is low-only about 2% for an 8192 × 64-bit SRAM.