This work presents a novel configurable two-stage inverter-based ultra-low-power (ULP) OTA with digitally adjustable output stage for dynamic adjustments of gain-bandwidth product, (GBW) and average slew rate (${\mathbf {SR}}_{\mathbf {av}}$). This approach improves both the flexibility of the OTA compared to conventional DC-biased designs, providing a reliable solution for mitigating process, voltage, and temperature variations. The circuit is designed using standard cells in a 180-nm CMOS process and is then fully synthesizable. Experimental measurements are executed over process corners and voltage variations. The proposed OTA works at nominal 0.3-V power-supply voltage and consumes only 1.2 nW, while exhibiting 56-dB DC gain and 7.6-kHz maximum GBW with 5-pF capacitive load.

Exploiting the recently introduced concept of the Dickson charge pump (CP) used as a signal amplifier, this paper introduces a new class of gain boosted amplifiers that can be obtained when the small-signal model of the charge transfer device depends on the input signal. The original design equations are enhanced, resulting in a new effective equivalent model for amplifiers based on CP circuits. The analytical predictions are validated by simulation and experimental results on a silicon prototype implemented in 65-nm standard CMOS technology.

The paper introduces a four-stage operational transconductance amplifier (OTA) targeting ultra-low-power and ultra-low-voltage applications. The proposed circuit comprises a simple while effective compensation topology which entails a single Miller capacitor and an RC parallel block at the output of the third stage. Implemented in a standard CMOS 180-nm technology and powered at 0.3 V, this work uniquely benefits of power consumption reduction of a factor 39X-33,333X and a rail-to-rail dynamic range when compared with previous 4-stage OTAs. In addition, the proposed solution improves the state-of-the-art of high-gain multi-stage bulk-driven OTAs exhibiting a larger DC gain (>17.9 dB), a 1.9X improved gain-bandwidth product under higher maximum capacitive load (2.85X) and, hence, an increase of the F OMSof more than 4.4X.

A nanopower, buffered CMOS voltage reference designed to operate across the entire industrial temperature range (from$- 40~^{\circ }$C to$125~^{\circ }$C) and with an input voltage range from 1.2 to 5 V (automotive applications) is presented. The solution provides 390 mV at$20~^{\circ }$C and is implemented in a standard BCD technology featuring 160-nm CMOS devices. It is characterized by an average temperature coefficient of 200 ppm/°C, a line sensitivity (LS) of 0.138%/V, and a power supply rejection of −83 dB at 100 Hz. In addition, the circuit occupies a die area of 0.146 mm2 (with the reference circuit alone covering 0.043 mm2) and maintains a highly stable current consumption of around 45 nA across various process and input voltage conditions (25 nA for the reference circuit alone) while providing a maximum output current of$630~\mu $A with a load regulation of 0.016 mV/$\mu $A.

This work proposes a very-low quiescent current corner-compensated analog LDO with reconfigurable topology for multiple output voltage values, and its pW-powered voltage reference. The design of the proposed LDO has been optimized for sub-1V for battery-less systems that exhibit an average power consumption from hundreds nW up to hundreds of μW. Measurement results on a 180nm standard CMOS technology prove the effectiveness of the design strategy and validate the working principle of the LDO. The proposed analog LDO can work with a supply voltage down to 0.55-0.6V, consuming only 15-nA of quiescent current and it shows 6.4x lower FoMt (7.5x for FoMtv) compared with similar prior art.

This study presents a low-voltage bulk-driven CMOS operational transconductance amplifier (OTA) operating in the subthreshold region designed to drive loads up to 10 nF, which is the largest value for this class of amplifiers. To meet this goal, the solution exploits the body terminal of various active devices leveraging local positive feedback to enhance the input transconductance gain and implementing dynamic threshold voltage control in the output transistors. This, along with a Slew Rate Enhancer section, significantly improves the OTA current driving capability. Experimental measurements conducted on a prototype, implemented in a 60-nm technology and supplied from 0.35 V, confirm the expected performance demonstrating a SR of 1.1 V/ms for a 10-nF load with a limited quiescent current consumption of 1.4$\mu$A.

This paper introduces a novel design approach and a prototype of a fully on-chip charge pump (CP)-based boost converter for integrated circuits powered by single solar cells. Measured performance proves the effectiveness of the proposed architecture and design strategy. Comparison with other integrated energy harvesting solutions based on CPs shows that the proposed solution occupies the lowest area with a comparable power conversion efficiency. Moreover, the power density is about 2.5 times higher than the best value reported.

This work presents a 78.5-nA, 115-ppm/°C temperature coefficient, switched capacitor current reference for batteryless and US-powered implantable biomedical devices. It is also characterized by the presence of a trimming network that allows compensating the PVT variations. The circuit is designed in a 28-nm Bulk CMOS technology provided by TSMC and full post-layout characterization is provided. The proposed solution shows a 75.8-% power utilization, an overall power consumption of about 62 nW when operating under 0.6-V power supply the lowest area occupation compared with previous arts, making the circuit well suitable also for ultra-low power and sub-1V sensor nodes for the Internet-of-Things.

This paper presents and discusses two Dickson charge pumps that are capable of working with a supply voltage lower than the MOS threshold voltage and are particularly suited for energy-constrained applications. Specifically, the paper includes a theoretical analysis of a previous topology introduced by the authors, and then it discusses a novel topology which solves drawbacks of the previous one. The paper also includes a comparison with other conventional topologies, namely the latched and the four-phase charge pumps, that shows the inherent advantage of the proposed solutions also in the range of input values higher than the MOS threshold voltage. 2-, 4-, and 6- stage versions of the conventional and proposed CPs have been fabricated in a 65-nm standard CMOS technology having a MOS threshold voltage equal to about 440 mV. Experimental results confirm the analytical predictions since the proposed topologies work at input voltage equal to 300 mV with a current load equal to$20~\mu \text{A}$and also confirm the advantages of the two proposed solutions in terms of settling time, output current drivability and output power density for voltages slightly higher (450 mV) than the MOS threshold voltage.

Feedback amplifiers consisting of multiple gain stages are used to establish highly accurate buffered/amplified signals that can drive a wide range of capacitive load (CL). This article models, analyzes, and presents the measurement results of a high-gain four-stage operational transconductance amplifier (OTA) that is able to handle a wide range of CL up to infinity. In addition to local compensation capacitors and nulling resistors in the intermediate stages, two high-speed feedback loops made by parallel Miller capacitors and current buffers provide Miller compensation and the consequent pole-splitting in the lower CL range. The dominant pole is made dependent on the CL for the higher CL range, enabling the maintenance of the stability conditions up to infinite CL. The proposed amplifier was integrated into a 65-nm CMOS technology, consuming 140-$\mu$A static current under a 1.2-V supply and an active area of 0.0086 mm$^{{2}}$. A dc gain greater than 100 dB was also perceived with a unity-gain frequency (UGF) of 4.09, 2.01, and 0.27 MHz for 4.7, 10, and 100-nF load capacitors, respectively. The average slew rate (SR) is 0.59 V/$\mu$s, when the OTA is formed as a buffer targeting the CLs higher than 4.7-nF.

A bulk-driven operational transconductance amplifier (OTA) suitable for ultralow-power and ultralow-voltage applications is described. The amplifier exploits local positive feedback in the first stage to increase its transconductance. The OTA entails a single Miller capacitor for frequency compensation, thus saving area occupation and improving frequency performance. As a distinctive feature of the proposed solution, the OTA is stable for capacitive loads higher than 5 pF. Implemented in a 65-nm standard CMOS technology, the proposed solution occupies an area of 10.6$\cdot$10$^{-3}$mm$^{2}$and is powered from 0.3 V, with a total quiescent current equal to 8.5$\mu $A. Experimental measurements show a gain–bandwidth (GBW) product of 1.65 MHz (0.81 MHz) with a phase margin (PM) equal to 70$^{\circ}$(71$^{\circ})$when driving a 50-pF (150-pF) load, featuring the best figures of merit compared to other multistage sub-1-V OTAs in the literature.

In this paper it is proposed and explored the use of the Dickson charge pump (CP) to amplify time-variant signals. The study has been carried out through a theoretical analysis that provides an in-depth comprehension of the behavioral equations and the main design metrics commonly used to evaluate the performance of amplifiers. Starting from the analytical models, we show the conditions upon which the CP can be modeled with an equivalent small signal circuit and can amplify a signal. Then, assuming the CP working in the widest operative conditions, small-signal, large-signal and noise analysis are carried out. The results have been validated by extensive simulations and measurements on a proof of concept using a 130 nm CMOS technology.

A CMOS differential amplifier cell for minimum supply requirements is presented. The solution uses transistors in strong inversion and an original biasing scheme that exploits the bulk terminals of the transistor pair to accurately set the quiescent current and provide common-mode control. As a result, we avoid the use of the tail current source adopted in traditional differential stages. An implementation based on an auxiliary switched-capacitor network used in the feedback control loop is proposed and theoretically examined. Measurements on a prototype fabricated in a standard 0.35- mum technology (with threshold voltages around 0.5 V) and powered with 1.2 V show an error in the bias current of about 15% with respect to the expected value. It was found that the obtained overall performance is comparable to that of a traditional long-tailed differential pair that uses a higher supply of 1.5 V.

A novel frequency compensation technique for three-stage amplifiers is introduced. Compared to the traditional reversed nested Miller compensation strategy, the proposed one exploits two active stages already included in the amplifier topology, thus no extra circuitry for its implementation is needed. The technique allows to remove the right-half-plane zero and generates a left-half-plane zero, improving the phase margin. Design equations using the phase margin as design parameter are carried out. The proposed technique is used to design, using a standard CMOS 0.35-mum technology, a 2-V three-stage amplifier driving a 500-pF load. The amplifier dissipates 0.24 mW at DC and achieves a 1.75-MHz gain-bandwidth product