Spectral testing and linearity testing are two important categories in ADC testing. The sampling clock quality is a crucial factor in ADC spectral testing. The cumulative clock jitter of the sampling clock generates power leakage in the fundamental component of the ADC output spectrum, and the random clock jitter increases the noise floor of the ADC output spectrum, which corrupts the spectrum result of the ADC. This paper proposes a new algorithm to accurately estimate the ADC specifications despite sampling clock jitter. The ADC output sequence is divided into small segments. Each segment is paired with another one, such that their initial phases match with each other the best. By analyzing the difference of each segment pair, the noise power is separated from clock jitter and is estimated accurately. In each segment, by removing the estimated local cumulative jitter, the leakage due to cumulative clock jitter is removed, correct harmonic and non-harmonic spur information is obtained. Simulation and measurement results comparing with the standard test methods corroborated the accuracy and robustness of the new solution. This method significantly relaxed the stringent test requirements on high precision sampling clock and dramatically reduced the test cost and complexity, which offers potential for low cost on-chip testing.

Since 2004, Texas Instruments and Portland State University have collaborated to develop and deploy test data analytical methods for use in a variety of applications, including quality screening, burn-in minimization, high cost test replacement and/or removal, and operations monitoring. In this paper, key findings amassed during this time are summarized.

Location Averaging is a nearest electrical neighbor method of Statistical Outlier Screening (SOS) for screening outliers from probe test data used at Texas Instruments (TI). Location Averaging is sensitive to variances, not only from die parametrics, but also the test solution. Variance in outlier counts specific to Location Averaging that present either a strong commonality in the test solution, or test pattern on the wafer map, or both, can be indicative of a problem in the test solution. Analysis of outlier counts provides a method of monitoring and maintaining the test solution through data-driven techniques to optimize execution through the reduction of downtime and excursions.

In this paper, a novel Bayesian model fusion (BMF) method is proposed for test cost reduction based on wafer-level spatial variation modeling. BMF relies on the assumption that a large number of wafers of the same circuit design (e.g., all wafers from the same lot) share a similar spatial pattern. Hence, the measurement data from one wafer can be borrowed to model the spatial variation of other wafers via Bayesian inference. By applying the Sherman-Morrison-Woodbury formula, a fast numerical algorithm is derived to reduce the computational cost of BMF for practical test applications. Furthermore, a new test methodology is developed based on BMF and it closely monitors the escape rate and yield loss. As is demonstrated by the wafer probe measurement data of an industrial RF transceiver, BMF achieves 1.125× reduction in test cost and 2.6× reduction in yield loss, compared to the conventional approach based on virtual probe (VP).

Manufactured devices have a diverse performance/quality profile due to process variations. Devices with superior performance and quality are of higher value while the rest can be sold for a lower price. Separating manufactured devices according to their performance is defined as quality/performance binning and is a very effective way of lowering average device cost. In this manner, devices that have below average quality are not wasted and therefore device cost is reduced. Quality binned devices share the same design and typically go through the same manufacturing process and even the same test process. After the testing step, they are binned according to different sets of performance criteria, typically according to the customer specifications. The bin a device falls depends on the process and typically does not match the amount requested by the customers because of uncertainty (variation) of the process. In this work, we present a multi-bin quality-oriented adaptive test method that efficiently classifies the devices according to the desired quality criteria and minimizes the overall test time.

A realistic, as opposed to fixed pessimistic end-of-life method to identify paths that are at-risk to excessive degradation due to aging is presented. It uses library cell grading information to assess the cells/instances for their sensitivity to parametric degradation.

The discovery of patterns and correlations hidden in the test data could help reduce test time and cost. In this paper, we propose a methodology and supporting statistical regression tools that can exploit and utilize both spatial and inter-test-item correlations in the test data for test time and cost reduction. We first describe a statistical regression method, called group lasso, which can identify inter-test-item correlations from test data. After learning such correlations, some test items can be identified for removal from the test program without compromising test quality. An extended version of this method, weighted group lasso, allows taking into account the distinct test time/cost of each individual test item in the formulation as a weighted optimization problem. As a result, its solution would favor more costly test items for removal from the test program. We further integrate weighted group lasso with another statistical regression technique, virtual probe, which can learn spatial correlations of test data across a wafer. The integrated method could then utilize both spatial and inter-test-item correlations to maximize the number of test items whose values can be predicted without measurement. Experimental results of a high-volume industrial device show that utilizing both spatial and inter-test-item correlations can help reduce test time by up to 55%.

Efficiency of test compaction is very important for production test time minimization. Poor test compaction methods either result in long test time or low test quality for analog and mixed-signal circuits. One of the most important factors in test compaction quality is accuracy of the representation of process statistics. Accurate representation is challenging since process characteristics are not stationary; thus, they need to be updated to maintain a reliable test quality level over the complete production run. Previous work in test compaction either does not take process shift into account or uses simplistic updating methods to avoid the cost of process relearning. In this paper, we propose an efficient relearning method that tracks changes in the process state of devices and generates a compact test list using relearned information for production test. The focus of this paper is production test of packaged devices. We model the mechanics of the process shift with a transformation function. We use information from a set of packaged devices of a reference (characterized) wafer to predict the characteristics of devices coming from other wafers using a very small number of learning samples. Fitting the transformation function enables us to map outdated process information to the up-to-date process information. We demonstrate the performance our method and compare it with previously published work using large scale production data of two distinct mixed-signal circuits. We show that our method maintains superior DPPM levels over large numbers of wafers and lots.

We present an adaptive test flow for mixed-signal circuits that aims at optimizing the test set on a per-device basis so that more test resources can be devoted to marginal devices while passing devices that are not marginal with less testing. Cumulative statistics of the process are monitored using a differential entropy-based approach and updated only when necessary. Thus, process shift is captured and continuously incorporated into the analysis. We also include provisions to identify potentially defective devices and test them more extensively since these devices do not conform to learned collective information. We conduct experiments on an low-noise amplifier circuit in simulations, and apply our techniques to production data of two distinct industrial circuits. Both the simulation results and the results on large-scale production data show that adaptive test provides the best tradeoff between test time and test quality as measured in terms of defective parts per million.

In present day technology, the design of reliable systems must factor in temporal degradation due to aging effects such as Negative Bias Temperature Instability (NBTI). In this paper, we present a methodology to estimate delay degradation early at the Register Transfer Level (RTL). We statically analyze the RTL source code to determine signal correlations. We then determine probability distributions of RTL signals formally by using probabilistic model checking. Finally, we propagate these signal probabilities through delay macromodels and estimate the delay degradation. We demonstrate our methodology on several benchmarks RTL designs. We estimate the degradation with <10% error and up to 18.2x speedup in runtime as compared to estimation using gate-level simulations.

The virtual probe (VP) technique, based on recent breakthroughs in compressed sensing, has demonstrated its ability for accurate prediction of spatial variations from a small set of measurement data. In this paper, we explore its application to cost reduction of production testing. For a number of test items, the measurement data from a small subset of chips can be used to accurately predict the performance of other chips on the same wafer without explicit measurement. Depending on their statistical characteristics, test items can be classified into three categories: highly predictable, predictable, and un-predictable. A case study of an industrial RF radio transceiver with more than 50 production test items shows that a good fraction of these test items (39 out of 51 items) are predictable or highly predictable. In this example, the 3σ error of VP prediction is less than 12% for predictable or highly predictable test items. Applying the VP technique can on average replace 59% of test measurement by prediction and, consequently, reduce the overall test time by 57.6%.

This paper introduces an adaptive test method to dynamically control test flow and test contents with continuous per die updates of test fail rates. The method employs Bayesian statistics to model a separate fail rate for each test. Test reordering and elimination is based on statistics of these predicted fail rates and is naturally monitored by a wafer based reset. Wafer sort test response data for two 65nm integrated circuit products is used to demonstrate this method. Test time reductions of about 30% are achieved with quality levels within industry expectations.

Outlier devices behave differently from the majority of the devices and are considered to be potentially defective. Identifying outliers has many applications in test, including defect filters for alternate test, and setting pass/fail limits for automotive domain. In previous work, outliers have been identified using single dimensional and/or static methods which does not exploit information efficiently. In this work, we propose an adaptive multidimensional outlier analysis method that combines the information of multiple measurement parameters and judiciously selects only information rich parameters to maximize detection probability. Furthermore, the proposed method continously updates to track process shift to enable adaptation to the evolving processes. The proposed method can be integrated within an existing test framework to improve test quality with little or no additional test time cost. In this context, we integrate our technique with an adaptive test framework and show that the method enables improved test quality.

Adaptive testing is a generic term for a number of techniques which aim at improving the test quality and/or reducing the test application costs. In adaptive tests, the test content or pass/fail limits are not fixed as in conventional tests, but dependent on other test results of the currently or previously tested chips. Part-average testing, outlier detection, and neighborhood screening are just a few examples of adaptive testing. With this Embedded Tutorial, we are offering an introduction to this topic, which is hot in the test community, to the wider DATE audience.

Despite their small size, analog/mixed-signal circuits start with an extensive set of parameters to test for. During production ramp up, most of these tests are dropped using statistical analysis techniques based on the dropout patterns. While effective in reducing the number of tests, this approach treats each device in an identical manner. As the statistical diversity of the devices increases due to increasing process variations, such homogeneous testing approaches may prove to be inefficient. After a number of initial measurements, device-specific information is available, which can provide clues as to where in the process space that device falls. Using this information, the test set for each device can be tailored with respect to its own statistical information. In this paper, we present an adaptive test flow for mixed-signal circuits that aims at optimizing the test set per-device basis so that more test resources can be devoted to marginal devices whereas devices that fall in the middle of the process space are passed with less testing. We also include provisions to identify potentially defective devices and test them more extensively since these devices do not conform to learned collective information. We conduct experiments on an LNA circuit in simulations and apply our techniques to production data of two distinct industrial circuits. Both the simulation results and the results on large-scale production data show that adaptive test provides the best trade-off between test time and test quality as measured in terms of defective parts per million.

Quality improvement and cost reduction in the overall IC manufacturing and test processes are being continuously sought. Outlier screening methods can address both of these needs. As technology scales, it has become increasingly difficult to screen outliers without excessive Type I or II errors. Hundreds of parameters are collected at wafer probe, but there lacks a systematic way of selecting outlier screens. In this paper we describe a statistical approach to both identify outliers and select beneficial screening parameters more effectively. Results on a 90 nm design to reduce the burn-in fails are described.

The Williams and Brown model has long been the gold standard for estimating test escape rate as a function of yield and fault coverage. However, today's test programs have a number of differing test types, often with overlapping failing unit detections. This paper details the development of a method which permits test escape rate predictions based on product yield and multiple overlapping test coverages.

At-speed testing is becoming crucial for modern very-large-scale-integration systems, which operate at clock speeds of hundreds of megahertz. In a scan-based test methodology, it is common to use a transition delay fault model for at-speed testing. The launching of the transition can be done either in the last cycle of scan shift [launch-off-shift (LOS)], or in a functional launch cycle that follows the scan shift and precedes the fast capture [launch-off-capture (LOC)]. The LOS technique offers significant advantages over the LOC in terms of coverage and pattern count, but since it requires the scan enable (SEN) signal to change state in the time period of one functional clock cycle, considerable engineering resources are required to close the timing on the SEN signal. Low-cost testers will not be able to provide the at-speed SEN signal as required by the LOS technique. We propose a scan-based at-speed methodology that generates “local” SEN signals that are guaranteed to switch in one functional clock cycle even when the external SEN signal does not change state at functional speed. Our technique is based on encapsulating the SEN control signal in the scan test data. A new scan cell, which is called the last transition generator, must be inserted in every scan chain for generating internal SEN signals. The proposed method is robust, practical, and readily implemented using commercial tools available today.

The sub-100 DPPM numbers in deep submicron is being built, but the tolls is fairly steep. Traditional methods using simple fault models and pass/fail testing have to be abandoned in favor of probabilistic and statistical approaches. Tests generated for simple fault models detect numerous types of real defects. The cost is increased tester time, though this can be mitigated somewhat by the application of relatively new on-chip pattern compression schemes.

It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.

At-speed test has become a requirement in IC technologies below 180 nm. Unfortunately, test mode switching activity and IR-drop present special challenges to the successful application of structural atspeed tests. In this paper we characterize these problems on commercial ASICs in order to understand how to implement more effective solutions. 1

Semiconductor manufacturers aim to deliver products to market within a short span of time in order to gain market share. There are several facets of introducing a product to market - design, manufacturing, first silicon debug, and ramp to volume. Of these, first silicon debug time contributes significantly towards reduced product cycle time if it can be kept short. In this paper, we discuss the infrastructure, design tools, test tools and debug tools required to achieve successful first silicon debug. We describe a production device that employs these infrastructure requirements, thereby demonstrating the advantages of following the guidelines. The paper also highlight the ill effects of not adhering to the guidelines.

If you look at the mix of papers published at ITC over the last ten years or so, there does appear to be a large swing away from board test topics and towards more IC-oriented technical papers. Why is that? Could one argue that board test became a solved problem after the introduction of the IEEE 1149.1 standard [1]? Hardly, since that original standard, as useful as it has proven to be, was still deficient in a number of areas and is being actively extended even today. The most notable recent extensions are the 1149.4 analog interface and the proposed P1149.6 extension for high speed digital signals. As an ASIC vendor, we work with many different companies on implementing ASICs in a variety of applications. Often, given the choice, our customers would opt not to implement boundary scan on their designs. It’s not clear if this is indicative of the perceived difficulty in using the approach, a lack of familiarity with the tools involved, the use of other more desirable solutions, or some combination of the above. Clearly, boards are not going untested. So, either via JTAG or other means, solutions exist for board level testing. But, if board manufacturers are opting for non-1149.1 test procedures, the question remains, why do we not see more active research in this area? There are probably at least two reasons:

The semiconductor industry as a whole is growing increasingly concerned about the possible presence of delay-inducing defects. There exist structured test generation and application techniques which can detect them, but there are many practical issues associated with their use. These problems are particularly acute when using low cost test equipment. In this paper, we describe an overall approach for implementing scan-based delay testing with emphasis on low-cost test.

Scan based test techniques offer a very efficient alternative to achieve high fault coverage when compared to functional pattern testing. As circuit sizes grow ever larger, test data volume and test application time grow unwieldy even in the very efficient scan based designs. The Illinois Scan Architecture is a low cost alternative to conventional scan. In this paper, we present the first ever reported case study of the effectiveness of the Illinois Scan Architecture on an industrial circuit.

Power consumption during scan testing is becoming a concern. Circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption. This paper presents a scheme for reducing power and provides analysis results on an industrial design.

The order in which the various test types are applied can have an impact on the overall efficiency of the test operation. Furthermore, the speed at which the tests can be executed and the latency of defect detection are also important factors. In this paper, we evaluate an exhaustive set of test orderings over a variety of assumed execution parameters to analyze their effects on overall tester time consumption.

Defect diagnosis in random logic is currently done using the stuck-at fault model, while most defects seen in manufacturing result in bridging faults. In this work we use physical design and test failure information combined with bridging and stuck-at fault models to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). We build on top of the existing mature stuck-at diagnosis infrastructure. The performance of the CAFDM software was tested by injecting bridging faults into samples of a Streaming audio controller chip and comparing the predicted defect locations and layers with the actual values. The correct defect location and layer was predicted in all 9 samples for which scan-based diagnosis could be performed. The experiment was repeated on production samples that failed scan test, with promising results.

High levels of integration have complicated the entire IC manufacturing process. Crucial steps such as ramp to volume production and yield improvement techniques are being challenged. In this paper, a diagnostic system that has been developed and deployed into a production environment is presented. Experiments conducted demonstrating the value of the diagnostic tool and its limitations are presented.

Traditional yield enhancement efforts have long relied on memory bitmapping techniques. With the industry marching toward system-on-a-chip technology, the importance of logic products has increased exponentially. This necessitates the development of innovative techniques to perform logic yield enhancement. In this paper the authors present a novel technique that can be used to perform logic yield enhancement. The paper concentrates on logic bitmapping at Texas Instruments. Results obtained from a few production samples of a graphics processor are also presented.

Monolithic ICs are growing so large that tester capacity is rapidly becoming a problem. There are also a number of "stored pattern" test methods which vie for limited tester resources. From a quality perspective, how do we best allocate tester memory or time? In this paper, the SEMATECH Test Methods data are used to examine this important question.

For many years, non-target detection experiments have been simulated by using AND/OR bridges or gross delay faults as surrogates. For example, the defective part level can be estimated based upon surrogate detection when test patterns target stuck-at faults in the circuit. For the first time, test pattern generation techniques that attempt to maximize non-target defect detection have been used to test a real, 100% scanned, commercial chip consisting of 75 K logic gates. In this experiment, the defective part level for REDO-based patterns was 1,288 parts per million lower than that achieved by DC stuck-at based patterns generated using today's state of the art tools and techniques.

The stuck-at fault has weathered at least two major revolutions in the manufacture of electronic components, the transition from tubes to solid state, and the move from bipolar to MOS technologies. It has been applied successfully in all three domains. It seems unlikely that future digital technologies will invalidate the use of the model. In conclusion, as long as the stuck-at fault model remains useful, it should not be abandoned in favour of other defect models. Investigations into new models and test techniques should continue, with the idea that they will probably be used to complement existing stuck-at-based methodologies.

Automated fault diagnosis based on the stuck-at fault model is not always effective. This paper presents practical experiences in applying a bridging fault based diagnosis technique to a TI ASIC design. Results are presented for units into which known bridging defects have been introduced via a focused ion beam (FIB) machine.

Effective bridging fault diagnosis requires reducing the (/sub 2//sup n/) number of bridging faults to a handful of candidates. A preliminary step can reduce the O(n/sup 2/) candidates to a manageable O(n) candidates by using layout information to eliminate those bridging faults that are very unlikely to be shorted together. This step removes from consideration those faults that match the fault signature but are physically impossible. However, sometimes-perhaps due to issues of intellectual property or because the degree of information stored about a circuit changes over its lifecycle-the physical design of the circuit is not available, and the number of nodes is too large to explicitly consider all pairs. In this paper we present two ways to provide successful diagnoses without access to physical information. The second method produces optimal diagnoses under our ranking criteria. Either technique can be used in conjunction with information extracted from the physical design to allow for diagnoses of much larger circuits than previously possible.

The SEMATECH "Test Methods Evaluation" study, Project Number S-121, is an experiment to determine the relative merits of several test methodologies often used by SEMATECH member companies and other IC manufacturers. Conclusions drawn from the experiment thus far have indicated that each test methodology uniquely detects defects. This experimentation and analysis would not have been possible outside a consortium setting such as SEMATECH. Its conclusions may affect other major segments of the industry, including ATE manufacturers, CAD vendors, and academia. This paper gives a brief overview of the experiment and summarizes its findings.

This paper describes an experiment in which various semiconductor test methodologies (stuck-fault, functional, delay and IDDq) are applied to an ASIC device. The goal of this project is to provide the data that will enable manufacturers to optimize their application of the various tests. This project was supported through SEMATECH (Project S-121, "Semiconductor Test Method Evaluation ").

The authors have integrated an AD system into the manufacturing flow for several key semiconductor products at Texas Instruments and have found the results to be both accurate and beneficial. The number of devices diagnosed to date remains relatively small, and further work will be required in order to perform AD on a larger scale. It is believed that AD system accuracy could be further improved through the use of nonclassical fault models such as bridging faults. Another useful feature would be the addition of a capability to generate patterns specifically for the purpose of distinguishing between faults, and to be able to generate those patterns "on the fly" as a device is being diagnosed. Finally, diagnosis based on IDDQ testing may prove to be an effective isolation technique.

ICs fabricated in increasingly deep submicron technologies are fundamentally shifting the problem areas on which to focus when testing these devices. Several major paradigm shifts are required in order for current test technologies to be extended to meet the challenges. In the past, chip sizes and operational speeds were such that numerous assumptions could be employed throughout the manufacturing test process which greatly eased pattern generation and application. Among those assumptions were: high stuck-at fault coverage is sufficient to guarantee high quality testing (other forms of testing can be neglected); the primary problem to be solved by test/DFT is defect detection (as opposed to defect isolation); parasitic effects can be ignored; test is a "stand-alone process". Unfortunately, it is being discovered that deep submicron technologies invalidate many of these assumptions. It is suggested that increased emphasis should be placed on design and test generation techniques for delay defects. The industry should formalize an acceptable metric to measure the coverage of such defects. When and where appropriate, test generation software should comprehend parasitic effects and thereby create tests which are more robust with respect to test application. A tester model should be put into place to more easily debug test patterns without the necessity of actual silicon. Finally, test generation cannot be performed in a vacuum. There is a great deal of commonality between the design requirements for the use of static timing analysis and those of testability. There also must be a merging of functionalities, such as between critical path identification and path-based test generation, to ease the use of these technologies.

The TMS320C80 is a programmable, parallel processing DSP. The test approach was an engineering mix of design for testability, test view creation, and verification. This mixture facilitated timely test generation and had other important benefits. We document the overall test methodology and the benefits derived therein.

The Texas Instruments TMS370 is in volume production. Sample manufacturing data has been collected to correlate stuck fault grades to the defect levels that would have been realized at those grades, at both the module and chip levels. Since the chip is composed of test isolatable modules, the data collected provide insights into the randomness of the distribution of failures among the modules. Further analysis shows good agreement between actual data and theoretical defect level model predictions. The data emphasize the need for hash fault coverages and correspondingly required DFT practices in today's era of "Six Sigma" quality targets.>

The nature of many problems related to testability requires detailed information about their underlying test parameters. These parameters are commonly referred to as controllability and observability. This research concerns exact measures of detectability, controllability, and observability to measure the relative importance of the latter two on the likelihood of the former. New functional methods for fault analysis are utilized which allow computations not previously possible; the empirical results presented here are an example of such an application.>

A new method, Difference Propagation, is proposed to analyze fault models in combinational circuits. It propagates Boolean functional information represented by ordered binary decision diagrams. Results are presented concerning exact detectabilities and syndromes for a set of benchmark circuits. The data suggest answers to open questions in CAD and represent the first data of this type for bridging faults. The information is shown to affect testable design as well as test generation.