Several efforts are currently underway to improve cloud-radiation parameterizations in Global Climate Models (GCMs) by incorporating statistical properties of the cloud field. Although some radiation parameterizations, which are already computationally costly, now incorporate subgrid scale variability in cloud properties, they are not yet capable of using this information in their calculations of the 3-D radiation fields. Before drastic changes are made to such algorithms to incorporate cloud-cloud radiation interactions, the impact of including realistic high-resolution cloud distributions on the shortwave fluxes should be assessed. This letter provides a framework for carrying out such assessments, including a new methodology that blends a stochastic radiative transfer model, high-resolution cloud fields from a mesoscale meteorological model, and a threshold and object identification technique applied to cloud water content fields. This process provides a link between the radiative fluxes calculated in GCMs, where clouds occur at a subgrid scale, and the highly resolved cloud fields in a regional climate model, which can provide cloud field statistics. Two case studies are described herein.

Path expressions were originally proposed by Campbell and Habermann [1] as a mechanism for process synchronization at the monitor level in software. Not unexpectedly, they also provide a useful notation for specifying the behavior of asynchronous circuits. Motivated by this potential application we investigate how to directly translate path expressions into hardware.

This paper identifies important steps in the design of a special purpose VLSI chip, and argues that the most crucial step is the design of the underlying algorithm. Because the algorithm determines the degree of parallelism and pipelining that is possible, it largely determines the performance of the chip. Furthermore, if the underlying algorithm has the right properties such as modularity and regularity, then the rest of the design should be routine and thus take little effort. These claims are supported by a concrete example—the design of an efficient pattern matching chip, which has been fabricated for testing.