In rice breeding, improving both crop yield and quality is of paramount importance. This study investigates key factors directly influencing yield, particularly the number of rice panicles and leaf width. We hypothesize that increases in panicle count and leaf width correlate positively with photosynthetic efficiency, thereby significantly affecting overall crop yield. To test this hypothesis, we aim to evaluate and select rice varieties exhibiting desirable phenotypes through targeted detection techniques. We utilize an enhanced DINO (self-distillation with no labels) model for detecting and segmenting rice panicles and leaves. The upstream component of our model functions as an unsupervised general feature extractor, learning rich visual features from a large dataset of unlabeled rice images. The downstream task consists of two branches: one for detecting the number of rice panicles and another for segmenting leaf areas. By combining these two branches, we are able to accurately assess the photosynthetic potential and reproductive capacity of rice plants. Experimental results demonstrate that our model outperforms traditional methods in both panicle detection and leaf area segmentation, achieving higher accuracy and robustness. We conduct experiments on a newly curated dataset, RiceVar, which comprises over 50,000 images covering three rice cultivars captured under varied angles and backgrounds. Our proposed method achieves a mean average precision of 81.401 in panicle detection, a 14.7 point improvement over ResNet50, and a Dice coefficient of 84.322 and intersection over union of 82.186 in leaf segmentation, outperforming the EAPT model by 14.08 and 2.45 points, respectively. Moreover, our model remains stable under varying environmental conditions, highlighting its practical value for rice breeding applications. By precisely evaluating panicle count and leaf width, our model supports the selection of high-yield, high-efficiency rice varieties, contributing to the advancement of sustainable agricultural practices. The relevant code and data are available at https://github.com/xiaobeial/Semi-supervised-detection-and-segmentation-algorithm-for-efficient-rice-breeding.

The demand for precise timing continues to grow with the rapid development of smart cities, where intelligent transportation emerges as a critical application heavily dependent on accurate time distribution. Deterministic communication is anticipated to be a defining feature of nextgeneration mobile networks (6G), enabling end-to-end timecritical applications, and unlocking new possibilities for achieving end-to-end precise time synchronization as well. To cope with the challenge of delivering precise time synchronization across broader areas at a lower cost, this paper proposes a method to achieve end-to-end precise time synchronization by leveraging the deterministic characteristics of communication networks. Specially, the proposed approach adopts the Software-Defined Networking (SDN) paradigm to implement deterministic networking for the seamless integration of Time-Sensitive Networking (TSN) and cellular networks. Furthermore, to mitigate the impact of wireless channel uncertainties on synchronization accuracy, we propose a network delay measurement mechanism based on the principle of time redundancy, designed to reduce end-to-end network delay variation. Experimental results validate the effectiveness of the proposed method, demonstrating its capability to constrain the end-to-end relative time error of wired and wireless converged networks to the microsecond scale, without necessitating modifications to the existing network infrastructure.

Time-aware shaper (TAS) is key to enabling deterministic guarantees in time-sensitive networks (TSN), but it requires precise configuration for specific traffic scenarios. Dynamic traffic scenarios are increasingly commonplace with the rise of emerging applications, necessitating TAS reconfiguration to adapt to the changes in traffic. However, existing mechanisms primarily reconfigure TAS by generating a new gate control list (GCL) and transitioning to it, which may lead to temporary violations of bounds on delay or jitter, providing no persistently deterministic guarantees. In this paper, we propose a novel TAS reconfiguration mechanism with the virtual GCL (VGCL) to satisfy the demands of dynamic traffic while guaranteeing deterministic transmission. It implements TAS reconfiguration for dynamic traffic by embedding different VGCLs into the GCL, avoiding the need for the GCL transition. Thus, the reconfiguration problem is modeled as an embedding problem by using the VGCL and we develop algorithms to solve it. Experimental results demonstrate that our mechanism can well reconfigure TAS for dynamic traffic without the GCL transition, and increase the reconfiguration success rate in various scenarios compared with the existing approaches.

Memristor stateful logic is an effective way to achieve the real sense of in-memory computing in memristor-based crossbar array (MCBA). At present, the synthesis tools fall short in conducting a thorough exploration of the optimization potential pertaining to cascading stateful logic gates within MCBA, and the optimization objectives are relatively simple. In this article, a suit of stateful logic synthesis kit, named ILOSSS, improved from the previous LOSSS tool is achieved. Such kit includes two kinds of stateful logic synthesis processes for latency (corresponding to the High Time-Efficiency Synthesis Process (HTESP)) and energy (corresponding to the Low-Energy Synthesis Process (LESP)) optimization, respectively. Both of the synthesis processes are achieved by improving an existing synthesis process of MAGIC (SIMPLER-MAGIC) to support multiple stateful logic gates and inserting a post-processing stage with a well-developed automated optimization algorithm to reduce the number of the gates of the netlist with a corresponding purpose. Comparing to the standard SIMPLER-MAGIC tool, the HTESP achieves arithmetic mean improvements of over 23% in performance, and over 34% in effective lifetime under the EPFL benchmark suit which is also better than the results reported by the state-of-the-art MAGIC synthesis process (X-MAGIC). Meanwhile, the energy-delay product (EDP) of LESP has decreased by an average of over 10% and 42% compared to SIMPLER-MAGIC and HTESP, respectively.

Memristor stateful logic is an effective way to achieve the real sense of in-memory computing in memristor-based crossbar array (MCBA). However, cascading stateful logic gates in MCBA is a time-consuming sequential process comparing to the space-wise CMOS combinational logic circuit. It is essential to develop the automatic synthesis tool to achieve complex combinatorial logic function with less in-memory stateful logic gates. In this paper, a logic synthesis process based on several stateful logic gates (LOSSS) is achieved to enhance in-memory computing efficiency of the scene of single row/column-oriented stateful logic computing. First, multiply compatible two/one-input PMR-type stateful logic gates with the functions of NOR, OR and NOT are employed in the initial function synthesis to obtain a good start-point netlist. Then, a post-process stage is added in the flow to reduce the number of the gates of the netlist by developing an automated optimization algorithm of replacing some specific gate groups as the composite gates of IMP and ONOR with consideration of input overwritten. Finally, an improved mapping process is employed to cascade these stateful logic gates in a single row of the crossbar array with less device occupation. Comparing to the standard SIMPLER-MAGIC, LOSSS achieves arithmetic mean improvements of over 23% in performance, and over 34% in effective lifetime under the EPFL benchmark suit which is also better than the results reported by the state-of-art MAGIC synthesis process (X-MAGIC).

Time-sensitive networking (TSN) is very appealing to industrial networks due to its support for deterministic transmission based on Ethernet. The implementation of determinism typically demands for precise configuration on each output port of a TSN switch, which is complex and time-consuming. Moreover, many emerging industrial applications bring dynamic scenarios (e.g., in real-time Internet of Things), thus the configurations should change adaptively as application requirements change to provide continued determinism. In this paper, we propose a deep reinforcement learning (DRL) based adaptive configuration scheme in Software-defined time-sensitive networking (SD-TSN). The SD-TSN is a network architecture that integrates the determinism guarantees of TSN and flexible network management of software-defined networking (SDN). Based on the capability of SD-TSN, the proposed configuration scheme exploits DRL to learn from interacting with the environment for adaptive configuration. Experimental results demonstrate the effectiveness of our scheme in dynamic scenarios.

Time-aware shaper (TAS) is key to enabling deterministic transmission guarantees in Time-Sensitive Networks (TSN), but requires precise configuration for a specific traffic scenario. Traffic dynamics change scenarios are gradually increasing with the development of Industry 4.0, necessitating reconfiguring TAS to guarantee persistence determinism. However, previous reconfiguration mechanisms are mostly reconfiguring TAS by modifying the gate control lists (GCLs) to adapt to changes in traffic, which may incur a temporary violation of bounds on delays or jitter with undesirable consequences. In this paper, we propose a novel reconfiguration mechanism with the virtual GCL (VGCL) to satisfy new traffic requirements by embedding different VGCLs into the GCL, such that implements TAS reconfiguration while avoiding the GCL modification. Then we develop an incremental VGCL embedding (IVE) algorithm to determine reconfiguration details. Experimental results show that our approach can reconfigure TAS well for dynamic traffic without modifying the GCL while guaranteeing high schedulability in different scenarios.

The need for precise timing is increasing with the development of the smart city, and intelligent transport is a key application that often relies on the distribution of accurate timing. Existing time synchronization solutions cannot adequately meet the precise timing needs for practical applications in intelligent transportation. Global Navigation Satellite Systems (GNSS) signals, for instance, can be obstructed, weakened, or deflected in urban canyon environments. While certain sectors like telecommunications and smart grids have successfully adopted IEEE 1588 for high-precision time synchronization, its dependence on standalone networks and limited application within local area networks poses challenges when catering to the wide-ranging and mobile demands of intelligent transportation applications. This paper categorizes the time synchronization requirements of intelligent transport and proposes a time synchronization scheme over converged networks, which separates time transmission and precision compensation based on software-defined networking (SDN) principles, and makes it possible to provide precise timing for intelligent transport devices, including on-board units (OBUs) and roadside units (RSUs), over wired and wireless communication networks. Experimental results indicate that the proposed scheme achieves a relative time error of less than 1.2 microseconds over the converged networks.

The emerging applications in vertical industries generate diverse time-critical traffic flows with bounded delay requirements. Time-Sensitive Networking (TSN) enhances the traditional Ethernet by using Time-Aware Shaper (TAS), providing delay guarantees for traffic flow transmission. However, the fixed scheduling granularity of physical queues in TAS can bring an obstacle for the flow isolation in per-flow scheduling, such as the complex computing and configuration. This paper proposes a method of Virtual Queues-based Time-Aware Traffic Scheduling (VQ-TATS) in Software-Defined Time-Sensitive Networking (SD-TSN). SD-TSN is a networking architecture that integrates the determinism guarantees of TSN and flexible network resource allocation of Software-Defined Networking (SDN). Through the capability of SD-TSN, the physical queues resource is virtualized for VQ-TATS. VQ-TATS includes the VQ clustering and VQ mapping stages. VQ clustering aggerates virtual queues to adapt to the scheduling granularity of TAS. VQ mapping builds the relationship between virtual and physical queues and generates the gate control list of TAS. The clustering and mapping algorithms are also designed to perform VQ-TATS. The evaluation in an industrial control use case shows the effectiveness of the proposed method in schedulability and runtime.

Time synchronization is a key technology in time-sensitive networking (TSN) to support deterministic data transmission with bounded latency, low delay jitter, and zero congestion loss guarantee. TSN uses IEEE 802. IAS protocol to achieve time synchronization. The asymmetry of the propagation link, clock drift, and limited node clock frequency resolution limit the TSN time synchronization performance improvement. In this paper, we propose a scheme for enhancing the time synchronization performance of TSN and design a method to enhance the TSN time synchronization accuracy by precisely measuring the deviation of the start frame delimiter (SFD) identification signal of the frame initiator from the local received clock signal, and taking the measured value as the compensation amount. Furthermore, we introduce a time correction algorithm in the compensation process. The corresponding development implementation is completed in FPGA, and a test environment is constructed for experimental verification. The experimental results obtain a time synchronization accuracy of 7.5ns, and the synchronization accuracy is even better than 5ns after introducing the time correction algorithm.

Applications such as virtual/augmented reality, autonomous systems, and telemedicine require delay-bounded transmission. This paper combines the software-defined network (SDN) paradigm and proposes an integrated solution for topology construction and routing (TCR). First, the solution gives a delaybounded constraint for adding valid links, which can be adapted to various topology construction methods. Then, topology discovery, resource management, flow management, and route selection are performed in the orchestration and configuration plane. TCR enables time-sensitive network management and configuration with flexibility. The performance of the TCR is evaluated in a typical industrial network topology. The experimental results show that the TCR can effectively reduce the average path length (APL), guarantee bounded delay, and is beneficial for load balancing.

Resistive random-access memory (ReRAM)-based crossbar array (RCA) is a promising platform to accelerate vector-matrix multiplication in deep neural networks (DNNs). There are, however, some practical issues, especially device variation, that hinder the versatile development of ReRAM in neural computing systems. The device variations include device-to-device variation (DDV) and cycle-to-cycle variation (CCV) that deviate the devise resistance in the RCA from their target state. Such resistance deviation seriously degrades the inference accuracy of DNNs. To address this issue, we propose a software-hardware compensation solution that includes compensation training based on scale factors (CTSF) and variation-aware compensation training based on scale factors (VACTSF) to protect the ReRAM-based DNN accelerator against device variation. The scale factors in CTSF can be flexibly set for reducing accuracy loss due to device variation when the weights programmed into RCA are determined. For effectively handling CCV, the scale factors are introduced into the training process for obtaining variation-tolerant weights by leveraging the inherent self-healing ability of DNNs. Simulation results based on our method confirm that the accuracy losses due to device variation on LeNet-5, ResNet, and VGG16 with different datasets are less than 5% under a large device variation by CTSF. More robust weights for conquering CCV are also obtained by VACTSF. The simulation results present that our method is competitive in comparison to other variation-tolerant methods.

An increasing number of Industry Internet of Things (IIoT) applications put forward the requirements for strict time synchronization and accurate time service from providers. In order to indicate the time service performance of the Internet Time Service Providers (TSPs) on user sides, we build an Internet time service monitoring system which can obtain the real-time data of time service through the Internet. The monitoring system records the time service’s performance from three major categories: NTP pool projects, National Metrology Institutes and Commercial Organizations. After that, we propose three service metrics, in terms of Availability, Stability and Accuracy, to evaluate the performance of time service provided by TSPs. On the other hand, a novel anomaly detection algorithm is proposed to gather the statistics of abnormal data and then remove the abnormal data. Experimental results show that 56 TSPs’ availability are more than 95%. It indicates that a longer transmission path results in a lower availability. The further analyzed results also denote that the link hops have no correlations of Availability, Stability and Accuracy. Moreover, the relationship between Stability and Accuracy is positively correlated.

Edge Computing (EC) has been proposed as a promising approach to fulfil the requirements of high bandwidth and ultra‐latency of mobile applications. However, existing researches on resource allocation only consider the computing resource of mobile devices and EC servers, while ignored the constraint of the networking resources once spreading applications among multiple EC servers via wireless and wired networks. Fibre‐Wireless access networks (FiWi) combine the huge bandwidth of optical fibre networks and flexible access of wireless networks to address the above issue and bridge the coexistence of multiple EC servers. They propose a Virtualisation‐based Architecture converging EC over FiWi (VAECFW) to centralise control and allocate networking and computing resources for serving requested services. In addition, they study the problem of resource allocation of EC over FiWi and propose two algorithms Revenue‐based Virtual Network Embedding (R‐VNE) and Balanced Central Processing Unit Resource Allocation with Virtual Network Embedding (BCRA‐VNE). Simulation experiments show that the services acceptance ratio is increased about 35% under their proposed architecture, and the average service requests bandwidth utilisation of R‐VNE is increasing from 50 to 66%, and the BCRA‐VNE is from 37 to 48%. The two algorithms not only achieve higher revenue but also get better profit rate.

With the enhanced development of networks, management system has to meet different kinds of security and invulnerability challenges, such as unexpected changes of topology caused by targeted attack or failure, which disrupts existing traffic. In order to reduce the negative impact of topological changes on traffic, the topology needs to be adjusted in a short period of time before the recovery of the attacked node or the failure node. With the substantial flexibility offered by virtual network to implement new topology, how to calculate the new topology efficiently has become a hot topic of research. To achieve the goal, we present a novel algorithm based on the closeness centrality (CC) of nodes to reconfigure the topology in response to unexpected topological changes. The Efficient Topology Reconfiguration algorithm (ETR) reconfigures the topology by adding a fraction of links to the currently existing topology to satisfy the network requirements set before. We demonstrate the performance of the ETR algorithm and compare it with other algorithms. The experimental results show that we reconfigure the topology with the ETR algorithm more efficiently under targeted attacks and failures while ensuring the performance of reconfiguration.

Software Defined Network (SDN) mixed with Virtual Network (VN) is considered as a future network architecture-Virtual Software Defined Network (VSDN) for enhancing the network planning and the resource usage of networks. However, how to assign VSDN resources to virtual links and virtual network topologies efficiently and on- demand is one of the most challenging problems of any VSDN solution. This paper first proposes a dynamic bandwidth management architecture based on VSDN, and then presents an overall virtual network request scheduling model and finally proposes an optimization algorithm for dynamic bandwidth allocation, namely, K- Shortest Path based on Historical Path Data (HP-KSP). By taking advantage of historical path data and the real-time bandwidth of the physical network links, our HP-KSP algorithm adds a path allocation mechanism to the bandwidth management. Independent of the number of physical nodes, simulation results show that our proposed approach outperforms existing K-Shortest Path (KSP) and K-Shortest Path based on Disjoint Paths (DPKSP) algorithms since our HP-KSP satisfies more virtual requests which are mapped onto the same substrate and has higher QoA (Quality of Algorithms).

With the rapid development of networks, a great number of applications supported by fifth generation (5G), such as the Tactile Internet, ought to be provided with low delay. Hence, decreasing the delay of networks has attracted plenty of attention from academia. In this paper, we focus on constructing scale-free topologies toward low delay for the Core Network (CN) of 5G. The small average path length (APL), a notable property of the small-world, can be reflected in the Barabási-Albert model (BA model). The small APL indicates that packets can be routed from the source to the destination through fewer switches, decreasing the nodal processing delay. We modify the BA model to construct scale-free networks with smaller APL to reduce the nodal processing delay caused by switches. Furthermore, we generalize the BA model with the delay of propagation. In addition, we compare our proposed model with the BA model in terms of the performance of delay and we analyze the effect of the parameters on delay. Experiments validate that the improvement of the model is affected by the total number of nodes in the network and the index parameter. Experimental results also show the delay of scale-free networks constructed by our proposed model is lower than the original BA model.

Multipath algorithms except Equal-Cost Multi-Path(ECMP) which has been widely used in networks are difficult to apply, because multipath provisioning is more complex at cross layers and multipath routing need to get all nodes' information. To address the dilemma, this paper proposes a multipath network virtualization implementation scheme with Software Defined Networking (SDN) and Network Function Virtualization (NFV). In this scheme, SDN schedules network resources in a global view for selecting multiple paths and computing weight of each path, and NFV provides computing and storage resources to split flow, add tag, recover flow, to name a few. This paper also proposes a multipath algorithm for elephant flow with network virtualization. Besides, we build an experimental platform based on OPNFV and SDN, and conduct experiments under this experimental platform. The results show that our proposed algorithm applied on multipath network virtualization experimental platform has superior performance than ECMP applied in networks without virtualization.

As a combination of fiber networks' huge available bandwidth and wireless networks' ubiquity and mobility, the fiber-wireless (FiWi) access network is considered as a promising network architecture for future networks. The wireless subnetwork of FiWi networks is responsible for users' Internet access and connected to back-end fiber subnetwork. Inheriting from pure wireless networks, the wireless subnetwork is also vulnerable to the factors in surrounding environment such as noise, mutual interference of different users and etc. Although fiber links are quite good, they are not perfect. When a fiber link is long enough, the signal fading can not be ignored which may make receiver receive a false packet. The interference in wireless subnetworks and the signal fading in fiber subnetworks severely affect the quality of service in FiWi networks. In this paper, a code-based packet recovery mechanism in FiWi access networks is proposed. Based on the XOR coding, a packet which contains recovery message is generated by sender after sending several normal packets. The recovery packet follows these normal packets. Our packet recovery mechanism makes the receiver be able to cope with the situation of one packet loss, rather than request the sender to retransmit. The recovery packet generating algorithm and the packet recovery algorithm are also presented. Through extensive numerical simulation, we discuss the cost of packet recovery mechanism and compare its performance with the alternative without packet recovery mechanism.

Fiber-wireless (FiWi) access networks, which are a combination of fiber networks and wireless networks, have the advantages of both networks, such as high bandwidth, high security, low cost, and flexible access. However, with the increasing need for bandwidth and types of service from users, FiWi networks are still relatively incapable and ossified. To alleviate bandwidth tension and facilitate new service deployment, we attempt to apply network virtualization in FiWi networks, in which the network’s control plane and data plane are separated from each other. Based on a previously proposed hierarchical model and service model for FiWi network virtualization, the process of service implementation is described. The performances of the FiWi access networks applying network virtualization are analyzed in detail, including bandwidth for links, throughput for nodes, and multipath flow transmission. Simulation results show that the FiWi network with virtualization is superior to that without.

Wireless mesh networks (WMNs) are thought by many as one of the most potential networking technologies for next generation wireless networks. However, WMNs' performance is vulnerable to the interference in the environment. In order to get higher bandwidth and data transmission rate, fiber links are used to assist the communication in WMNs. The new network is called fiber aided wireless mesh networks (FAWMNs). There are two kinds of nodes in FAWMNs: those which only support wireless link and those which simultaneously support wireless link and fiber link. Correspondingly, there are two kinds of manners for packets transmission in FAWMNs: (i) several single wireless links manner; (ii) the wireless-fiber- wireless link manner. These make the packet transmission have multiple path choices. In this paper, a throughput model based on prior link probability for FAWMNs is proposed. The results demonstrate that the introduction of fiber links can bring some positive changes on the distribution of links and a noticeable promotion for the throughput of the node in FAWMNs.