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Jing-Ling Yang

dblp:88/3073 · DBLP profile ↗
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5ranked-venue papers
5as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 5 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 81% Hardware reliability and fault tolerance · 9% Integrated circuit design · 9%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
design for testability		 0.112008
State-Sensitive X-Filling Scheme for Scan Capture Power Reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation
hardware verification and test		 0.112008
State-Sensitive X-Filling Scheme for Scan Capture Power Reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › hardware verification and test
low-power testing		 0.112008
State-Sensitive X-Filling Scheme for Scan Capture Power Reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › hardware verification and test › low-power testing
scan test power reduction		 0.112008
State-Sensitive X-Filling Scheme for Scan Capture Power Reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › hardware verification and test › test data compression
x-filling		 0.112008
State-Sensitive X-Filling Scheme for Scan Capture Power Reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Integrated circuit design
asynchronous circuit design		 0.012004
A high-efficiency strongly self-checking asynchronous datapath · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004
Hardware reliability and fault tolerance
self-checking circuits		 0.012004
A high-efficiency strongly self-checking asynchronous datapath · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004

Methods — techniques the papers use, named apart from their topics

weighted switching activity minimization · 0.1probability-based x-filling · 0.1self-checking design · 0.0differential cascode voltage switch logic · 0.0
YearPublicationVenuePosition
2010 Parallel Interleavers Through Optimized Memory Address Remapping
abstract
This work presents mathematical models and collision-free exchange rules for a parallel interleaver, using which it develops an optimized memory address remapping (OPMM) scheme that enables a classic interleaver to be exchanged for a parallel interleaver readily and efficiently. Both analytic and experimental results demonstrate that the rate of annealing achieved using the OPMM approach is much faster than that achieved using the traditional memory address remapping (MM) method.
Jing-Ling Yang
 IEEE Trans. Very Large Scale Integr. Syst.1
2008 State-Sensitive X-Filling Scheme for Scan Capture Power Reduction
abstract
Based on the operation of a state machine, this paper elucidates a comprehensive frame for probability-based primary-input-dominated X-filling methods to minimize the total weighted switching activity (WSA) during the scan capture operation. Experimental results demonstrate that the proposed approach significantly reduces both average and peak WSAs.
Jing-Ling Yang, Qiang Xu 0001
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2004 A high-efficiency strongly self-checking asynchronous datapath
abstract
This work examines the inherent self-checking (SC) property of latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic. Consequently, a highly efficient SC dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve SC. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design.
Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2003 Design for Self-Checking and Self-Timed Datapath
abstract
This work examines the inherent self-checking property of a latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic (DCVSL). Consequently, a highly efficient self-checking (SC) dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve self-checking. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design.
Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun
 VTS1
2002 A Totally Self-Checking Dynamic Asynchronous Datapath
abstract
This paper investigates the inherent totally self-checking (TSC) property of one type of dynamic asynchronous datapath based on Differential Cascode Voltage Logic (DCVSL). As a result, a totally self-checking dynamic asynchronous datapath architecture is proposed. It is simpler than other similar approaches and represents a new approach to fault tolerant design.
Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun
 Asian Test Symposium1