Performance results are given for use of a weighted random pattern test generator, WRP, on ten benchmark designs. Deterministic (DET) and WRP tests created for single stuck faults are compared in their ability to detect shorts and transition faults. The WRP is able to generate a test for all the single stuck faults detected with a state-of-the-art deterministic pattern generator; WRP is highly efficient in CPU time required for full stuck fault test pattern generation; both DET and WRP achieved high net-to-net shorts fault coverage on a sample of ten designs; and WRP had significantly higher ( approximately=11%) transition fault coverage than obtained with DET for the same sample.>

A heuristic method for generating large-scale integration (LSI) test patterns is described. In particular, this paper presents a technique for generating statistically random sequences to test complex logic circuits. The algorithms used to obtain a set of tests by means of weighted logic signal variations are included. Several techniques for assigning these weights and for varying them are discussed on the basis of the primary algorithm. Also described is a means of obtaining a minimal number of test patterns. This approach has proved successful in obtaining fault-detecting patterns.