Demo Data from VLDB 2026 / reviewers in the wild / expert
Vi Cuong Chan
dblp:88/6052
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 50% Electronic design automation · 50% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › multi-objective optimization
area-time tradeoff |
0.0 | 1 | 1996 | Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays · FPGA 1996 |
Reconfigurable computing and FPGAs
FPGA architecture |
0.0 | 1 | 1996 | Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays · FPGA 1996 |
Reconfigurable computing and FPGAs › FPGA architecture
hierarchical FPGA |
0.0 | 1 | 1996 | Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays · FPGA 1996 |
Electronic design automation
physical design |
0.0 | 1 | 1996 | Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays · FPGA 1996 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate ArraysabstractNo abstract available. Vi Cuong Chan, David M. Lewis |
FPGA | 1 |