Demo Data from VLDB 2026 / reviewers in the wild / expert
Christoffer Amlo
dblp:88/6610
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1999
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 56% Parallel and multicore computing · 44% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
multithreading |
0.0 | 1 | 1999 | The Superthreaded Processor Architecture · IEEE Trans. Computers 1999 |
Parallel and multicore computing › speculative parallelization
thread-level speculation |
0.0 | 1 | 1999 | The Superthreaded Processor Architecture · IEEE Trans. Computers 1999 |
Compilers and program optimization
parallelizing compiler |
0.0 | 1 | 1999 | The Superthreaded Processor Architecture · IEEE Trans. Computers 1999 |
Processor architecture and microarchitecture
superscalar processor |
0.0 | 1 | 1999 | The Superthreaded Processor Architecture · IEEE Trans. Computers 1999 |
Methods — techniques the papers use, named apart from their topics
execution-driven simulation · 0.0compiler-directed speculation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1999 | The Superthreaded Processor ArchitectureabstractThe common single-threaded execution model limits processors to exploiting only the relatively small amount of instruction-level parallelism that is available in application programs. The superthreaded processor, on the other hand, is a concurrent multithreaded architecture (CMA) that can exploit the multiple granularities of parallelism that are available in general-purpose application programs. Unlike other CMAs that rely primarily on hardware for run-time dependence detection and speculation, the superthreaded processor combines compiler-directed thread-level speculation of control and data dependences with run-time data dependence verification hardware. This hybrid of a superscalar processor and a multiprocessor-on-a-chip can utilize many of the existing compiler techniques used in traditional parallelizing compilers developed for multiprocessors. Additional unique compiler techniques, such as the conversion of data speculation into control speculation, are also introduced to generate the superthreaded code and to enhance the parallelism between threads. A detailed execution-driven simulator is used to evaluate the performance potential of this new architecture. It is found that a superthreaded processor can achieve good performance on complex application programs through this close coupling of compile-time and run-time information. Jenn-Yuan Tsai, Christoffer Amlo, David J. Lilja, Pen-Chung Yew |
IEEE Trans. Computers | 3 |