This paper presents a multipath wide-bandwidth magnetic current sensor based on Hall effect. To simultaneously achieve wide bandwidth, minimal ripple and small area, the system incorporates a non-spun filter-free main path with offset elimination through a continuous-time compact auxiliary path. The auxiliary path cancels the main path offset via feedforward, alleviating the need for area-consuming blocking capacitor or DC servo loop. Therefore, the chip occupies only 1.52 mm2. To suppress ripple in the auxiliary path induced by spinning current, a ping-pong switch-capacitor (PPSC) filter is proposed which mitigates ripple by sampling and averaging in the forward path, with the system achieving a residual ripple of$4.1~{\mu }$T. Compared with the state-of-the-art Hall sensor, it achieves$5{\times }$bandwidth improvement,$2{\times }$ripple reduction while occupying$5{\times }$less area.

Light detection and ranging (Lidar) is usually enabled by Single-Photon Avalanche Detector (SPAD) sensors which may be falsely triggered by ambient light. Coincidence detection can suppress the ambient light at the cost of the lateral resolution. A$64\times 64$SPAD image sensor with coincidence detection is proposed for Lidar. A main-sub time-to-digital converter (TDC), in which the main TDC is used for timestamping the coincidence window and the sub-TDC is used for timestamping the event within the coincidence window, is proposed to avoid the loss of the lateral resolution at a small power cost. A delay-locked loop (DLL) is adopted to generate an analog voltage for maintaining the length of the coincidence window against process-voltage-temperature (PVT) variations. A TDC code correction circuit is proposed to reduce the probability of TDC inter-segment errors to 0.7%. The SPAD image sensor is based on the 3D integration of a SPAD array with a ROIC. The ROIC chip is fabricated in a$0.18\mu $m CMOS process. Driven by a 250 MHz multi-phase clock and a 100 MHz data readout clock, the chip achieves a maximum frame rate of 35.7 kframe/s, a timing resolution of 0.5 ns, and a timing range of$2\mu $s. The typical average power consumption of the ROIC is 135.5 mW (@21.7 kframes/s). The measured differential nonlinearity (DNL) ranges from -0.74 to +0.82 least significant bit (LSB), and the integral nonlinearity (INL) ranges from -0.95 to +0.95 LSB.

In this paper, an RC relaxation oscillator exhibiting robust performance over an extended temperature and supply range is proposed. By incorporating a digitally-assisted calibration loop, the design eliminates the errors from switch on-resistance, comparator offset and propagation delay. Fabricated using a 180 nm bipolar-CMOS-DMOS (BCD) process technology, the oscillator operates at a frequency of 7MHz with the supply sensitivity of 870 ppm/V across a voltage range of 1.7 to 4.2 V. The evaluation of 40 untrimmed samples achieved an average temperature coefficient (TC) of 52 ppm/$^{\circ}$C from$-$40$^{\circ}$C to 165$^{\circ}$C, with the worst observed TC being 81 ppm/$^{\circ}$C. The aging test results indicate small deviations of 0.3% and 11% in the oscillation frequency and its TC, respectively. Furthermore, the direct power injection test confirms its reliability and robustness with a maximum error of oscillation frequency of 6.4%.

This paper proposes a MOSFET-only voltage reference using the standard 1.2-V MOSFET based on the 65nm CMOS technology, which achieves a power supply voltage operating range of 0.65 V to 2.5 V and the line regulation is 443μV/V. This work demonstrates the technique to achieve a low temperature coefficient and the function of offset voltage cancellation by ZTC-MOS, therefore, the effects of the offset voltage are eliminated. Monte Carlo simulation verifications were conducted based on the TSMC CMOS 65-nm process. Within the temperature range of -40 °C to 150 °C, the voltage reference is 507.4 mV and the temperature coefficient is 23.88ppm/°C in a 160-run Monte Carlo simulation. The overall power consumption is only 6.825 μW at 0.65 V supply under the TT corner and the temperature is set in the typical 27°C.

This paper introduces the utilization of a high-bandwidth rail-to-rail operational amplifier in switching converters, which opens the door to advancing switching converters towards higher switching frequencies. As the switching frequency increases, the signal within switching converters also rises, frequently surpassing the switching frequency itself. Consequently, a high-bandwidth amplifier becomes imperative. The proposed operational amplifier is fabricated using the 0.18-μm BCD process and integrated into the voltage-seconds balance circuit of a multi-mode four-switch buck-boost (FSBB) converter for validation purposes. Post-layout simulation results demonstrate that the amplifier achieves a bandwidth of 400 MHz with a quiescent current of 140 μA. Furthermore, the amplifier is applied in a high-frequency four-switch buck-boost converter to meet the demands of high switching frequencies. The input voltage for the four-switch buck-boost ranges from 150 V to 420 V, while the output voltage is maintained at 28 V. The excitation inductance value is only 5 μH. Simulation results demonstrate that the switching frequency can be enhanced to 2 MHz with the use of the high-bandwidth operational amplifier.

This paper presents a highly integrated MOSFET-only voltage reference with load driving capability realized in BCD 153 process, featuring a temperature coefficient of 1.6 ppm/°C from -40°C to 125°C, a high PSR of 127dB, low noise of 63 nV@1KHz for the voltage reference part, and a temperature coefficient of 1.35 ppm/°C from -40°C to 125°C, a PSR of 86dB and a load driving capability of 1 mA for the LDO part. Incorporating an ultra-low average temperature coefficient and load-bearing capability, the circuit under consideration also boasts a remarkably high power-supply rejection ratio. Furthermore, it exhibits commendable performance in terms of stability, noise characteristics, step response, and power consumption. The entire circuit utilizes only 21 MOS transistors, making it significantly compact compared to the conventional approach of combining a voltage reference module with an LDO module, thus resulting in substantial area savings. Besides, this circuit also maintains a stable static operating point across process variations, supporting straightforward migration to alternative processes with only minor adjustments.

This paper introduces a tri-loop capacitor-less low dropout regulator (CL-LDO) that achieves enhanced transient response and PSRR. In the primary loop, a Folded-Cascode operational amplifier is used as the error amplifier (EA) to achieve higher gain. The second loop adds feedback by detecting the output voltage and summing the results into the main loop. The third loop is current feedback loop (CFL), which can adaptively increase the power transistor gate current to achieve better transient response and lower power consumption. This CL-LDO is implemented using a BCD 0.18-μm process and operates at 1.8 V. It can efficiently convert the input voltage ranging from 0.7 V to 1.8 V into a stable output voltage of 0.6 V. Simulation results demonstrate that when the load current jumps from 100 mA to 200 mA (which is half the range of load current), an overshoot of 9 mV and an undershoot of 8 mV can be achieved. Additionally, this LDO can achieve a line regulation of 0.096 µV/mA and a PSRR (Power Supply Rejection Ratio) of 99 dB@10KHz. Moreover, the proposed LDO can handle a maximum load current of 200 mA effectively. Overall, the proposed CL-LDO design showcases improved transient response, PSRR, and line regulation, making it highly suitable for power-efficient System-on-Chip (SOC) applications.

This paper presents a RC relaxation oscillator with wide temperature range for automotive application. By using a digitally assisted calibration loop, the comparator offset and the loop delay are efficiently cancelled. With both reference voltage and current derived from the same ΔVBE-based bias circuit, the proposed design cancels leakage currents and makes the design insensitive to high-temperature. The oscillator was fabricated in a 180 nm BCD process, the oscillator operates at 7MHz and achieves a supply sensitivity of 870 ppm/V from 1.7 to 4.2 V at room temperature. Measurements on 40 samples without trimming show that it has an average temperature coefficient of 52 ppm/°C over a wide temperature range (-40°C to 165°C), with the worst case temperature coefficient of 65 ppm/°C.

There are two drawbacks in the previous tri-mode variable-frequency peak current mode (VFPCM) control for primary side regulation (PSR) double-clamp zero voltage switching (DCZVS) flyback converter: firstly, the current-sense resistor leads to non-negligible loss at high power and instability at high frequency; secondly, the previous tri-mode control suffers from poor dynamic performance and lacks accurate small-signal model in various control modes. In this paper, a novel sensorless current quad-mode control is proposed, which eliminates the current-sense resistor by input voltage feed-forward and improve the dynamic performance by introducing hybrid mode (HYM) and seamless mode-switch. In addition, a unified small-signal model of the four control modes is derived in the paper, which explains the high dynamic performance of the introduced HYM. The proposed sensorless current quad-mode control and the unified small-signal model are validated on a 16-50V input and 28V/320W output experimental prototype. Compared with the traditional tri-mode peak current mode control, the undershoot recovery time and overshoot recovery time of the proposed control scheme are reduced from 12ms to 2.0ms and 12ms to 1.6ms, respectively.

Benefiting from the gallium nitride (GaN) monolithic process, a half-bridge power IC can fully unlock the high-speed capabilities of GaN devices by integrating drive circuits and power switches on the same die. However, the high operating frequency of the GaN system puts forward higher requirements on the delay and reliability of the level shifter, which serves as the key component for the half-bridge power IC. This work develops a 200-V half-bridge monolithic GaN power IC, adopting an efficient and concise level-shifting solution to mitigate the adversely affecting on speed caused by the absence of p-type devices in GaN processes. In addition, this design includes a noise immunity enhancement structure, which eliminates$\text {d}V_{S}/\text {d}t$noise without compromising response time. The proposed GaN power IC has been implemented on a 1-$\mu \text{m}$GaN-on-silicon process, and experimental results have already been performed to verify its outstanding characteristics.

Because of the different working principles between conventional flyback and active-clamped flyback (ACF), the existing primary-side regulation (PSR) technology cannot be applied to ACF. And in order to achieve PSR of ACF, a low-cost digital sampling method based on the auxiliary winding of the transformer is proposed. In the conventional peak current mode (PCM) controlled ACF, the sampling resistor of primary current may introduce additional power loss, and high-frequency oscillations during sampling may reduce system's stability. Therefore, a digital feedback-feedforward control (FFC) method is proposed to eliminate the sampling resistor. The stability of the proposed control method and its influence on the dynamic response are studied. In addition, since GaN device has higher power loss during reverse conduction than its Si counterpart, design considerations of reverse conduction time of power switches are also discussed in this paper. All control methods and design considerations are verified on a GaN-based 12V-3A ACF, and the proposed control strategy is implemented by FPGA.

In the conventional peak current controlled active-clamped flyback converter, the primary side current sampling resistor Rsbrings many problems, among which the additional power consumption and instability are the most obvious ones. A new peak current control method without sampling resistor is proposed, which is suitable for both analog control (based on Analog IC or discrete components) and digital control (based on FPGA, ASIC, MCU, DSP, etc.). To exemplify, the FPGA-based digital control method is taken as case study, and the proposed control method is verified by experimental results. In a GaN-based 12V-3A ACF, the average efficiency is improved by upto 2.92% compared to the conventional peak current control methods. In addition, the dynamic response is greatly improved, and analysis is given to explain this improvement.