VLDB 2026 Research / reviewers in the wild / expert
Ya-Shian Li-Baboud
dblp:89/10385
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2018
0000-0003-3234-4345ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Embedded and real-time systems · 69% Electronic design automation · 27% Reconfigurable computing and FPGAs · 4% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Embedded and real-time systems
cyber-physical systems |
0.6 | 2 | 2018 | An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems · DAC 2018 A Testbed to Verify the Timing Behavior of Cyber-Physical Systems: Invited · DAC 2017 |
Electronic design automation › hardware verification and test
hardware verification |
0.3 | 1 | 2018 | An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems · DAC 2018 |
Embedded and real-time systems › runtime monitoring
runtime verification |
0.3 | 1 | 2018 | An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems · DAC 2018 |
Embedded and real-time systems › runtime monitoring
timing constraint monitoring |
0.3 | 1 | 2018 | An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems · DAC 2018 |
Embedded and real-time systems › timing constraints
timing constraint specification |
0.3 | 1 | 2017 | A Testbed to Verify the Timing Behavior of Cyber-Physical Systems: Invited · DAC 2017 |
Electronic design automation › hardware verification and test
timing verification |
0.3 | 1 | 2017 | A Testbed to Verify the Timing Behavior of Cyber-Physical Systems: Invited · DAC 2017 |
Reconfigurable computing and FPGAs
FPGA-based monitoring |
0.1 | 1 | 2018 | An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems · DAC 2018 |
Methods — techniques the papers use, named apart from their topics
timestamp temporal logic · 0.3verification testbed · 0.3analytical framework · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systemsabstractFormal specifications on temporal behavior of Cyber-Physical Systems (CPS) is essential for verification of performance and safety. Existing solutions for verifying the satisfaction of temporal constraints on a CPS are compute and resource intensive since they require buffering signals from the CPS prior to constraint checking. We present an online approach, based on Timestamp Temporal Logic (TTL), for monitoring the timing constraints in CPS. The approach reduces the computation and memory requirements by processing the timestamps of pertinent events reducing the need to capture the full data set from the signal sampling. The signal buffer size bears a geometric relationship to the dimension of the signal vector, the time interval being considered, and the sampling resolution. Since monitoring logic is typically implemented on Field Programmable Gate Arrays (FPGAs) for efficient monitoring of multiple signals simultaneously, the space required to store the buffered data becomes the limiting resource. The monitoring logic, for the timing constraints on the Flying Paster (a printing application requiring synchronization between two motors), is illustrated in this paper to demonstrate a geometric reduction in memory and computational resources in the realization of an online monitor. Mohammadreza Mehrabian, Mohammad Khayatian, Ahmed Mousa, Aviral Shrivastava, Ya-Shian Li-Baboud, Patricia Derler, Edward R. Griffor, Hugo A. Andrade, Marc Weiss, John C. Eidson, Dhananjay M. Anand |
DAC | 5 |
| 2017 | A Testbed to Verify the Timing Behavior of Cyber-Physical Systems: InvitedabstractTime is a foundational aspect of Cyber-Physical Systems (CPS). Correct time and timing of system events are critical to optimized responsiveness to the environment, in terms of timeliness, accuracy, and precision in the knowledge, measurement, prediction, and control of CPS behavior. However, both the specification and verification of timing requirements of the CPS are typically done in an ad-hoc manner. While feasible, the system can become costly and difficult to analyze and maintain, and the process of implementing and verifying correct timing behavior can be error-prone. Towards the development of a verification testbed for testing timing behavior in tools and platforms with explicit time support, this paper first describes a way to express the various kinds of timing constraints in distributed CPS. Then, we outline the design and initial implementation of a distributed testbed to verify the timing of a distributed CPS analytically through a systematic framework. Finally, we illustrate the use of the verified timing testbed on two distributed CPS case studies. Aviral Shrivastava, Mohammadreza Mehrabian, Mohammad Khayatian, Patricia Derler, Hugo A. Andrade, Kevin B. Stanton, Ya-Shian Li-Baboud, Edward R. Griffor, Marc Weiss, John C. Eidson |
DAC | 7 |
| 2017 | Timestamp Temporal Logic (TTL) for Testing the Timing of Cyber-Physical SystemsabstractIn order to test the performance and verify the correctness of Cyber-Physical Systems (CPS), the timing constraints on the system behavior must be met. Signal Temporal Logic (STL) can efficiently and succinctly capture the timing constraints of a given system model. However, many timing constraints on CPS are more naturally expressed in terms of events on signals. While it is possible to specify event-based timing constraints in STL, such statements can quickly become long and arcane in even simple systems. Timing constraints for CPS, which can be large and complex systems, are often associated with tolerances, the expression of which can make the timing constraints even more cumbersome using STL. This paper proposes a new logic, Timestamp Temporal Logic (TTL), to provide a definitional extension of STL that more intuitively expresses the timing constraints of distributed CPS. TTL also allows for a more natural expression of timing tolerances. Additionally, this paper outlines a methodology to automatically generate logic code and programs to monitor the expressed timing constraints. Since our TTL monitoring logic evaluates the timing constraints using only the timestamps of the required events on the signal, the TTL monitoring logic has significantly less memory footprint when compared to traditional STL monitoring logic, which stores the signal value at the required sampling frequency. The key contribution of this paper is a scalable approach for online monitoring of the timing constraints. We demonstrate the capabilities of TTL and our methodology for online monitoring of TTL constraints on two case studies: 1) Synchronization and phase control of two generators and, 2) Simultaneous image capture using distributed cameras for 3D image reconstruction. Mohammadreza Mehrabian, Mohammad Khayatian, Aviral Shrivastava, John C. Eidson, Patricia Derler, Hugo A. Andrade, Ya-Shian Li-Baboud, Edward R. Griffor, Marc Weiss, Kevin B. Stanton |
ACM Trans. Embed. Comput. Syst. | 7 |