A method of computing the error in the solution of the semiconductor current continuity equations as well as the error in the terminal currents is proposed. An appropriate error indicator is developed based on a divergence free upwinding (finite element) discretization. The grid used for discretization is adapted to the error in the solution by dynamically adding or removing grid points in order to improve the solution and thus the terminal currents. The examples indicate that it is sufficient only for a reverse-biased p-n junction to refine the grid according to the error in the Poisson equation. In the forward biased case, it is necessary to take into account the error in the current continuity equation in order to guarantee exact terminal currents.>

A grid refinement methodology suitable for arbitrary spatial dimensions and geometries is developed. Using just the structural description of a device-specified by the user or taken directly from the output of a process simulator-strategies for creating an initial grid are proposed, embodying whatever knowledge the simulator can have about how the solution will behave. After solving the PDEs, a grid is adapted by examining the local error involved in the discretization process. A set of procedures is proposed for this purpose and shown to be nearly optimal in terms of cost and efficiency. The key to implementing a robust and efficient scheme lies in the choice of a suitable error indicator; it is shown that some of the more obvious candidates can perform quite poorly. The initial grid construction and error indicator schemes are used to show how the full adaptation procedure works on some practical examples.>

The results of small-signal or transient analyses from a conventional device simulator (or measured data) can be combined with gradient-fitting techniques to produce smooth spline-based MOSFET charge models for circuit simulation. These techniques are also applicable to shape-from-shading problems. Results based on simulations of some small devices are presented. The comparative efficiencies of the small-signal and transient approach are discussed as well as the relation between the so-called small- and large-signal charges. The role of spline-based table models as against compact analytical models is considered.>

Robust computational techniques are presented for steady-state characterization of CMOS latchup via numerical device simulation. Of specific interest are efficient means of accurately evaluating knees in I-V characteristics, corresponding to latchup triggering and holding points. Making use of predictor-corrector continuation procedures and special initial-guess strategies, more than an order of magnitude improvement in computational efficiency is achieved over previous approaches. It is shown that for some latchup problems, these methods are essential due to their unique ability to trace characteristics that are multivalued in both I and V. Simulated results for both triggering and holding characteristics of a VLSI CMOS process are presented, from which primary structural dependencies are identified and new physical insight is obtained.>

In this paper, we present an overview of the physical principles and numerical methods used to solve the coupled system of nonlinear partial differential equations that model the transient behavior of silicon VLSI device structures. We also describe how the same techniques are applicable to circuit simulation. A composite linear multistep formula is introduced as the time-integration scheme. Newton-iterative methods are exploited to solve the nonlinear equations that arise at each time step. We also present a simple data structure for nonsymmetric matrices with symmetric nonzero structures that facilitates iterative or direct methods with substantial efficiency gains over other storage schemes. Several computational examples, including a CMOS latchup problem, are presented and discussed.

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