Pseudo-exhaustive testing (PET) offers a simple solution to testing complex circuits and systems [12].However, PET suffers long testing time for test generation and high area overhead of test hardware.The pipelined pseudo-exhaustive testing (PPET) achieves fast testing time with high fault coverage by pipelining test vectors and test responses among partitioned circuit segments [15].To reduce hardware overhead in PPET, a novel approach for implementing area-efficient PPET is presented.Circuit partitioning with retiming is used to convert designs for PPET.Experimental results show that this approach exhibits an average of 20% area reduction over non-retimed testable circuits.Our algorithm offers high utilization of existing flip-flops (FFs) and provides a framework for further performance optimization.