This paper examines modeling methods for applying model checking to game programs created with Unreal Engine 5 Blueprint scripting system (hereinafter UE5 Blueprint). UE5 Blueprint can visually describe game logic by combining various processing nodes, but as the size of the game grows, it becomes more difficult to find and fix bugs that prevent the game from progressing. In this paper, a formal verification technique, model checking, is used to automatically detect game logic bugs. We convert a game program created in UE5 Blueprint into an input model for the model-checker NuSMV to achieve verification by NuSMV. The proposed framework enables the automatic generation of models by formally defining the semantics of nodes. We also propose methods for data flow optimization and abstraction of variable domain for the purpose of reducing the number of states in the model. We applied the proposed method to a blueprint containing a typical flag management bug and confirmed that the bug was correctly detected by NuSMV. Furthermore, we show that the number of states can be significantly reduced by the optimization and abstraction.

Texture Discrimination and Quantification New Value Creation in Future Applications

A Field Programmable Sequencer and Memory (FPSM), which is an embedded memory based programmable device for peripherals on micro controller units, has been proposed at the architecture level. The FPSM functions not only as the memory but also as finite autonomous state transition controls independent of the CPU. In this paper, implementation on the LSI is described. The FPSM, fabricated using 180-nm 1-poly and 5-metal CMOS process technology, operates at the maximum frequency of 61.5 MHz with a power supply voltage of 1.8 V. The power consumption is 1.0 mW per programmable unit at the target frequency of 50 MHz. The performance of fundamental peripherals such as timers, shifters, serial receivers/transmitters, FIFOs and Pulse Width Modulations (PWM) are evaluated and verified.

In the development of a software system using UML, consistency between state machine diagrams and sequence diagrams is crucial. This study proposes a verification method for the consistency of a sequence diagram and state machine diagrams. The proposed method represents state machine diagrams and a sequence diagram as processes, and can verify the consistency by checking weak simulation of the processes. We confirms the method could detect inconsistency with an example.

This paper reports an efficient discrete cosine transform (DCT) processing for the JPEG algorithm using a massive-parallel memory-embedded SIMD matrix processor. The matrix-processing engine has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. For compatibility with this matrix-processing architecture, the conventional DCT algorithm has been improved in arithmetic order and the vertical/horizontal-space 1 dimensional (1D)-DCT processing has been further developed. Evaluation results of the matrix-engine-based DCT processing show that the necessary clock cycles per image blocks can be reduced by 87% in comparison to a conventional DSP architecture. The determined performances in MOPS and MOPS/mm are factors 8 and 5.6 better than with a conventional DSP, respectively. Moreover, the matrix-processing engine can reduce the number of total clock cycles for JPEG application about 49% in comparison to a conventional DSP architecture.

The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SoC) device test. This paper proposes putting the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM using low cost automatic test equipment (ATE). The area of the BISR is approximately 1.7 mm/sup 2/, about 2% of conventional SoC devices. Using an error storage table form contributes to realizing a small area penalty of the repair analysis function. e-DRAM functional test time was reduced about 20% less than the conventional method at wafer level testing. Moreover, the results of e-DRAM test and repair analysis using BISR is almost coincident with the conventional method.

Highly reliable testing techniques for ULSI memory with on-chip voltage down converter are established. These techniques are an accurate tuning of internal-Vcc (intVcc) and a wide operating margin test using a new stress mode. The accurate tuning of intVcc is achieved by the trimming method with the measuring of on-chip monitor device characteristics during repairanalysis tests. The wide operating margin test is executed using a new stress mode in which intVcc can be set to the various voltage conditions at the wafer sort tests (WT) and the final shipping tests (FT).

The authors describe a novel array architecture and its application to a 16-Mb DRAM (dynamic random-access memory) suitable for the line mode test (LMT) with test circuits consisting of a multipurpose register (MPR) and a comparator. The LMT can test all memory cells connected to a word line simultaneously. Testing with random patterns along a word line is easily realized by using the MPR as a pattern register after setting random test data in the MPR. Test time is reduced to approximately 1/1000. Owing to the MPR, the present LMT can achieve flexible testing with high fault coverage. The excess area penalty due to the circuits for the LMT is suppressed within 0.5% in application to the 16-Mb DRAM.>