Demo Data from VLDB 2026 / reviewers in the wild / expert
Jega A. Arulpragasam
dblp:89/2202
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1980
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 77% Embedded and real-time systems · 23% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › multiprocessor architecture
multiprocessor design |
0.0 | 1 | 1980 | Modular Minicomputers Using Microprocessors · IEEE Trans. Computers 1980 |
Embedded and real-time systems › embedded system design
microprocessor-based system design |
0.0 | 1 | 1980 | Modular Minicomputers Using Microprocessors · IEEE Trans. Computers 1980 |
Methods — techniques the papers use, named apart from their topics
breadboard implementation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1980 | Modular Minicomputers Using MicroprocessorsabstractThis paper presents the design and breadboard implementation of an experimental multiprocessor (mP) whose objectives were 1) to provide modularity of performance over the range of 0.2 million instructions/s (mips) to about 3 mips and 2) to optimize cost-performance over this selected range by exploiting the high technology of microprocessors and RAM's. Jega A. Arulpragasam, Robert A. Giggi, Richard F. Lary, Daniel T. Sullivan, Chin-Chang Wu |
IEEE Trans. Computers | 1 |