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VLDB 2026 Research / reviewers in the wild / expert

Haruhiko Matsunaga

dblp:89/3071 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 44% Distributed systems · 44% Integrated circuit design · 13%

Topics — the 1 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Distributed systems
contention resolution		 0.011991
A 1.5 Gb/s 8 X 8 Cross-Connect Switch Using a Time Reservation Algorithm · IEEE J. Sel. Areas Commun. 1991

Methods — techniques the papers use, named apart from their topics

simulation · 0.0
YearPublicationVenuePosition
1991 A 1.5 Gb/s 8 X 8 Cross-Connect Switch Using a Time Reservation Algorithm
abstract
An input queuing type switching architecture that uses a high-performance contention resolution algorithm to achieve high-speed and large-capacity cross-connect switching is presented. The algorithm, called the time reservation algorithm, features time scheduling and pipeline processing. The performance of this switch is evaluated by computer simulation. The throughput of this switch is about 90%, without requiring high internal operation speeds. Three LSI designs are developed to verify the feasibility of the high-speed switch. They are the input buffer controller LSI, the contention-resolution module LSI, and the space-division switching LSI. The LSIs were constructed with an advanced Si-bipolar high-speed process. Also, 8*8 cross-connect switching boards are introduced. The measured maximum port speed is 1.55 Gb/s.>
Haruhiko Matsunaga, Hitoshi Uematsu
 IEEE J. Sel. Areas Commun.1