This work presents the design of an on-line energy optimizer unit, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing elements (PE), tailored to the instantaneous workload information and is fully adaptive to variations in process and temperature. The circuit design borrows some of the basic principles of analog computation to continuously optimize the system-wide energy dissipation of multiple cores. The analogy between the energy minimization problem under timing constraints in a general task graph and the power minimization problem under Kirchhoffs current law (KCL) constraints in an equivalent resistive network is exploited

A broad range of new high-volume consumer applications require the availability of low-power, battery operated, wireless microsystems. These systems should conciliate a sufficient battery lifetime with reduced overall dimensions (including antenna), low cost and versatility. The design of such systems highlights many tradeoffs between performances, cost and power consumption. These considerations led our group to choose a direct-conversion scheme for a distributed sensors application. The key blocks for this architecture have been realized and measured in a 0.5 /spl mu/m CMOS technology, validating this approach. From these results, the total power consumption of a receiver operating in the 433 MHz ISM band is expected as low as 1.4 mW, under 1.2 V supply, for a sensitivity of -100 dBm and a 20 kbit/s data rate. The transmitter provides 9 dBm output power under the same supply voltage, with a 35% efficiency.

A broad range of high-volume consumer applications require low-power, battery operated, wireless microsystems and sensors. These systems should reconcile a sufficient battery lifetime with reduced dimensions, low cost and versatility. The design of such systems highlights many tradeoffs between performances, lifetime, cost and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V). These considerations are illustrated by design examples taken from a transceiver chip realized in a standard 0.5 /spl mu/m digital CMOS process. The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture. The circuit prototype operates in the 434 MHz ISM band and consumes only 1 mW in receive mode. It achieves a -95 dBm sensitivity for a data rate of 24 kbit/s. The transmitter section is designed for 0 dBm output power under the minimum 1 V supply, with a global efficiency higher than 15%.

Autonomous transceivers working in the ISM' UHF hands should meet both requirements of a long battery lifetime and a small overall volume, thus implying to cut the receiving power consumption down to less than 1 mW.Ultimately, this goal will only be reached by using original topologies and lowering the supply voltage down to single battery cell operation.A RF front-end and a power-amplifier (PA) designed for the 433 MHz European ISM band are presented.Both RF building blocks have been integrated in a standard 0.5 urn digital CMOS process with 0.65 V threshold voltages.The front-end includes an LNA and a downconverter mixer.It achieves a total double sideband (DSB) noise figure of 9 dB, with a dynamic range of 8.5 dB for a 60 kHz bandwidth, while dissipating only 250 uW at 1.2 V supply voltage.The PA includes two fully integrated Class A stages together with an output Class C amplifier.It achieves a +4 dBm output power with a 15 % overall efficiency under 1.2 V supply voltage.

An analogue electronic model of a cochlea was developed some years ago by R. F. Lyon using a cascade of filters. Combined with an analogue gradient descent circuit, such an artificial cochlea can be used to extract the Linear Predictive Coding (LPC) of the speech signal in continuous time. We propose in this article an analogue VLSI circuit implementing a so-called 'Cochlear LPC' (CLPC). We discuss the expected advantages of the CLPC, such as an optimal time-frequency resolution and the continuous time processing. Furthermore we present some speech recognition results obtained using a computer model of the CLPC pre-processing combined with an HMM classifier. These results compare favourably with those obtained from a standard LPC/HMM system.

Pulse frequency modulation (PFM) provides robust long-distance communication and event-driven access to the communication channel. A PFM demodulator small and simple enough to equip every cell of a large analog neural network is analyzed. The circuit can demodulate PFM signals with pulse rates as low as 1 kHz using the switched-capacitor technique. Measurement results from integrated demodulators are presented.

The design and application of low power VLSI-based circuits and systems is the focus of this forum and paper. Attention is placed on issues related to low power systems, such as choice of implementing semiconductor technology, power supply voltage (e.g., 3.3 V, 2.5 V, 1.0 V), CAD for low power design and synthesis, micropower digital and analog circuit design techniques, system architectural tradeoffs for low power, selective clocking for power management, low power synchronization strategies, self-calibration circuit techniques for low power, and low power figures of merit.>

An architecture for interchip communication among analog VLSI neural networks is proposed. Activity is encoded in a neuron's pulse emission frequency. Information is transmitted through the non-arbitered, asynchronous access of pulses to a common bus. The impact of collisions when the bus is accessed by more than one user is investigated. The information-carrying capability is assessed and the trade-off between accuracy of the transmitted information and attainable dynamic range is brought out in terms of simple global parameters that characterize the application. It is found that the proposed architecture is well suited for the kind of communication requirements associated to neural computation systems. A coding scheme aimed at pushing the system towards its theoretical performance is also presented and evaluated.