As conventional CMOS technology approaches power and performance limits, superconducting single flux quantum (SFQ) logic offers a path to high-speed, energy-efficient computing. However, SFQ circuits require cryogenic temperatures, introducing complex challenges in memory integration and data movement between thermal zones. This paper presents an end-to-end simulation framework for hybrid SFQ/CMOS-memory systems that accurately models processor, memory, and interconnect behavior across cryogenic $(4 \mathrm{~K}, 77 \mathrm{~K})$ and room temperatures $(300 \mathrm{~K})$. The framework integrates gate-level pipelined Rapid SFQ (RSFQ) RISC-V processors, temperature-aware CryoMEM memory models, and physically grounded interconnect latency models. The simulator facilitates cross-layer design space exploration across diverse parameters such as cache placement, interconnect stack selection, and granularity. These features allow the community to identify technological gaps and re-evaluate the bottlenecks in memory-compute throughput. Our evaluations highlight the critical interplay between processor frequency and memory bandwidth, demonstrate the speedup potential of 4K SFQ caches, and quantify the impact of cryostat cabling choices on system performance.

Shared memory system-on-chips (SM-SoCs) are ubiquitously employed by a wide range of computing platforms, including edge/IoT devices, autonomous systems, and smartphones. In SM-SoCs, system-wide shared memory enables a convenient and cost-effective mechanism for making data accessible across dozens of processing units (PUs), such as CPU cores and domain-specific accelerators. Due to the diverse computational characteristics of the PUs they embed, SM-SoCs often do not employ a shared last-level cache (LLC). Although covert channel attacks have been widely studied in shared memory systems, high-throughput communication has previously been feasible only by relying on an LLC or by possessing privileged or physical access to the shared memory subsystem. In this study, we introduce a new memory-contention-based covert communication attack,$\boldsymbol{MC}^{3}$, which specifically targets shared system memory in mobile SoCs. Unlike existing attacks, our approach achieves high-throughput communication without the need for an LLC or elevated access to the system. We explore the effectiveness of our methodology by demonstrating the tradeoff between the channel transmission rate and the robustness of the communication. We evaluate$\boldsymbol{MC}^{3}$on NVIDIA Orin AGX, NX, and Nano platforms and achieve transmission rates up to 6.4 Kbps with less than 1% error rate.

Ising machines model nature dynamics to solve nondeterministic polynomial time (NP) hard combinatorial optimization problems (COPs). Because physical systems can naturally minimize their energy, these Ising machines have higher efficiency as compared to von Neumann architectures. This makes Ising machines attractive for tackling complex optimization problems mapped to the Ising Hamiltonian. In this paper, a highly scalable CMOS-compatible Ising machine design is proposed that leverages ring oscillator coupling under second-order sub-harmonic injection locking (SHIL). The proposed design is smaller and faster as compared to the state-of-the-art based on initial findings. Unlike traditional designs that use external injection locking signals or bulky LC oscillators, the proposed approach integrates both spin representation and SHIL signal generation directly on-chip using lightweight ring oscillators. The phase readout process is simplified by utilizing XOR gates for efficient spin readout. The initial results, obtained through SPICE simulations on 28nm FDSOI technology, confirm the feasibility of the proposed design. This approach presents a compact high-speed Ising machine with potential applications in solving a wide range of NP-hard problems.

Superconductor-semiconductor interface circuits are integral part of connecting cryogenic classical and quantum computing systems with the room temperature electronics. Due to the cooling power constraints of cryogenic setups, the number of data transmission channels between temperature stages is often limited by the heat load of cables and connectors. As a result, a high data rate (throughput) per channel is desired for large-scale computing systems. The state-of-the-art superconductor-semiconductor interface circuits use a binary data format. In this work, a novel interface circuit is proposed that produces signals with pulse-amplitude modulation (PAM). As a case study, a PAM-4 SQUID (superconducting quantum interference device) stack interface circuit is developed. With four output voltage levels, the effective data rate can be doubled while keeping the same operating frequency. Alternatively, the number of cryogenic cables can be reduced by two times as compared to the conventional binary data links.

Pseudo-random number generators (PRNGs) are essential in a wide range of applications, from cryptography to statistical simulations and optimization algorithms. While uniform randomness is crucial for security-critical areas like cryptography, many domains, such as simulated annealing and CMOS-based Ising Machines, benefit from controlled or nonuniform randomness to enhance solution exploration and optimize performance. This paper presents a hardware PRNG that can simultaneously generate multiple uncorrelated sequences with programmable statistics tailored to specific application needs. Designed in 65nm process, the PRNG occupies an area of approximately 0.0013mm2and has an energy consumption of 0.57pJ/bit. Simulations confirm the PRNG's effectiveness in modulating the statistical distribution while demonstrating high-quality randomness properties.

Nature-inspired computation is receiving increasing attention. Various Ising machine (IM) implementations have recently been proven to be effective in solving numerous combinatorial optimization problems including maximum cut, low density parity check (LDPC) decoding, and Boolean satisfiability (SAT) problems. In this paper, a novel method is presented to solve SAT or MAX-SAT problems with a CMOS circuit implementation. The technique solves a SAT problem by mapping the SAT variables onto quantized capacitor voltages generated by an array of nodes that interact through a network of coupling units. The nodal interaction is achieved through coupling currents produced by the coupling units, which charge or discharge capacitor voltages, implementing a gradient descent along the SAT problem’s cost function to minimize the number of unsatisfied clauses. The system also incorporates a unique low-complexity perturbation scheme to avoid settling in local minima, greatly enhancing the performance of the system. The simulation results demonstrate that the proposed SKI-SAT is a high-performance and low-energy alternative that surpasses existing software-based SAT solvers by significant margins, achieving more than 10 times faster solution and over 300 times less power.

With the growing interest in emerging and upcoming quantum computers, it is important to consider possible hardware security vulnerabilities and countermeasures. This work proposes side-channel attacks targeting classical-quantum interface circuits in superconducting quantum computers. Particularly, a single flux quantum (SFQ) technology-based classical controller, which is a promising candidate for large-scale in-fridge qubit control and readout circuitry, is considered. We have uncovered a substantial side-channel leakage from superconducting interface circuits through the power supply variations. An attacker, who has access to room temperature electronics where the power is generated, can successfully decode certain information about various components within quantum computers.

Ising machines have shown great promise in solving combinatorial optimization problems (COPs) using nature-inspired computation with higher speed and efficiency over traditional von Neumann computing systems. CMOS-based implementations combine the maturity and scaling ability of CMOS with the efficacy of Ising machines. In this paper, a low-density parity-check (LDPC) decoding solution is implemented with a CMOS-based resistively-coupled Ising machine known as (QuBRIM), using multi-body interactions among CMOS-based Ising machine nodes for the first time. State-of-the-art CMOS-based Ising implementations currently utilize order reduction to solve problems with higher-than-quadratic terms. In this paper, a new mechanism is proposed to implement higher-than-quadratic terms on Ising machines without the need for order reduction. The proposed methodology is implemented and verified with CMOS technology using 45 nm Generic PDK (GPDK). High accuracy rates are reported for the LDPC decoder based on the proposed methodology, comparable to Normalized Min-Sum, Offset Min-Sum, and Layered Belief-Propagation decoders, with a bit error rate (BER) as low as$4 \times 10^{-8}$at a signal-to-noise ratio (SNR) of 4dB. Furthermore, the proposed LDPC decoder attains a normalized energy efficiency (NEE) of 1.29 pJ/bit/iteration, surpassing the state-of-the-art decoders by a minimum factor of 2.4 and as much as 7.6 times.

Cryogenic testing and verification of single-flux quantum (SFQ) circuits consist of various challenges, such as limited number of input–output pins, flux trapping, and cooling power constraints. Developing design for testability (DFT) techniques for SFQ circuits, which address these challenges, is an important research area. In this work, a built-in self-test (BIST) methodology of SFQ circuits is proposed, which focuses on a novel way of the readout of test signals by using side-channel leakage information. The side-channel leakage can exhibit the dependence of internal data (logical “1” and “0”) on the power consumption. By measuring the variations in the power supply of an SFQ circuit at room temperature, the information about internal test signal states can be extracted with the proposed BIST methodology. As a case study, a rapid SFQ (RSFQ) 4-to-2 priority encoder circuit is considered. The existing Josephson junction (JJ)-based stuck-at fault model is applied with the proposed BIST methodology. The proposed BIST design is compared with a conventional shift register-based readout circuitry. The proposed BIST design can provide 79% lower static power consumption and 65% lower layout area. In addition, other advantages and drawbacks of the proposed design are discussed, such as yield, number of pins, testing time, interpretation of test results, and hardware security.

The Ising-physical unclonable function (PUF) is a recent PUF structure formed of a network of APUFs inspired by the Ising model. A large challenge–response pair (CRP) space with high resilience against machine learning modeling attacks can be attained due to the unique arrangement. These advantages, however, are achieved at the cost of a large area overhead. In this article, a reconfigurable Ising-PUF is introduced with several new design knobs to generate a much larger CRP space within a smaller area. A 25% increase in the number of challenge bits can be achieved for a design that occupies 30% of the conventional Ising-PUF area. With the proposed lightweight area-efficient design, up to 5.6 times lower area per CRP can be achieved compared to the existing design. Several improvements are proposed that leverage the large design space, enabling dynamic tradeoffs between the area and CRP pool with the proposed flexible customization of Ising-PUFs. A detailed analysis of this improved design space is explored for different parameters. The state-of-the-art machine learning modeling attacks are investigated, and the Ising-PUF structure is shown to be resilient.

In this work, multiphase digital low-dropout (MP-DLDO) regulators are designed with resonant rotary clocks (ReRoCs) in order to improve on the tradeoff of conventional DLDOs between current efficiency and transient response speed. The proposed DLDOs are multiphased, coined MP-DLDOs, designed with a clock-gated control technique to provide high current efficiencies along with transient response improvements at GHz frequency levels. The multiple phases within the MP-DLDO are served with ReRoCs that provide: 1) a robust high-speed low-power resonant clock distribution solution for the synchronous elements in the multiphase DLDO architecture and 2) improve the transient response characteristics [dynamic voltage scaling (DVS) speed and voltage ripple] while saving power in the controller circuitry. The proposed MP-DLDOs are distributed across the chip to achieve low voltage ripple. SPICE simulations are performed on post-layout, parasitic-extracted models to evaluate the MP-DLDO architecture on open-source digital cores, with performance metrics that include the voltage ripple reduction, transient response speed improvement, and power savings in the control logic. The proposed MP-DLDO architecture, evaluated on an RISC-V design, demonstrates a DVS speed of 6.5 V/$\mu \text{s}$and an output voltage ripple of 21.1 mV (38% reduction when compared to a conventional DLDO) with a sampling frequency of 2 GHz.

The security and privacy of modern computing devices have become an important design metric with the unprecedented increase in the amount of personal information stored in the digital domain. Side-channel attacks have been demonstrated to be one of the primary threats for the security and privacy of these devices. Understanding the working principles of side-channel attacks has, therefore, become an important research problem. An efficient preprocessing technique is proposed in this work for an attack scenario where the amount of time to collect physical leakage (PL) and access to the device is limited. The proposed preprocessing technique utilizes different side-channel distinguishers to decrease the required number of PL measurements for a given success rate by enhancing the quality of the leakage signal. Two commonly used distinguishers, Pearson correlation and mutual information, are combined in this work. For the first time, combined distinguishers are used to improve the performance of both the preprocessing and the attack steps. The success rate of the proposed attack framework outperforms the conventional single distinguisher side-channel attacks by 33% and 30% for unmasked advanced encryption standard (AES) and masked AES, respectively.

The security implications of utilizing an on-chip voltage regulator as a countermeasure against fault injection attacks are investigated in this paper. The effect of the size of the capacitors and number of phases of the voltage regulator on the resilience of a cryptographic circuit against fault injection attacks are analyzed. The effectiveness of the proposed method in counteracting voltage glitch attacks is demonstrated with extensive simulations on the S-box of an advanced encryption standard~(AES) cryptographic algorithm. Using a single phase on-chip voltage regulator, the number of faults generated by a voltage glitch attack is reduced by 5.45% as compared to unprotected S-box, and by 91.82% when number of phases increases to 32.

To be able to meet demanding application performance requirements within a tight power budget, runtime power management must track hardware activity at a very fine granularity in both space and time. This gives rise to sophisticated power management algorithms, which need the underlying system to be both highly observable (to be able to sense changes in instantaneous power demand timely) and controllable (to be able to react to changes in instantaneous power demand timely). The end goal is allocating the power budget, which itself represents a very critical shared resource, in a fair way among active tasks of execution. Fundamentally, if not carefully managed, any system-wide shared resource can give rise to covert communication. Power budget does not represent an exception, particularly as systems are becoming more and more observable and controllable. In this paper, we demonstrate how power management vulnerabilities can enable covert communication over a previously unexplored, novel class of covert channels which we will refer to as POWERT channels. We also provide a comprehensive characterization of the POWERT channel capacity under various sharing and activity scenarios. Our analysis based on experiments on representative commercial systems reveal a peak channel capacity of 121.6 bits per second (bps).

For the first time, the combination of mutual information analysis and correlation power analysis is proposed to enhance the accuracy and success rate of side channel analysis. Using the k-nearest-neighborhood (KNN) algorithm, correlation power analysis is combined with mutual information analysis to classify various possible keys to two classes of correct and wrong keys. The advantage of the combination of the distinguishers is two fold. First, the accuracy of the estimation is enhanced due to availability of multiple possible values for the correct key. Second, the number of measurements required to disclose the correct key is reduced by combining the distinguishers. The effectiveness of combined distinguisher is verified by extensive simulations. The number of measurements required to perform a side channel attack with a success rate of 90% is improved, respectively, by 20% and 49%, as compared to individual correlation power analysis and mutual information analysis.

Digital low-dropout voltage regulators (DLDOs) have drawn increasing attention for the easy implementation within nanoscale devices. Despite their various benefits over analog LDOs, disadvantages may arise in the form of negative bias temperature instability (NBTI) induced performance degradation. In this paper, a simple and effective adaptive gain scaling (AGS) technique with a steady-state capture feature is proposed. AGS senses the steady-state output of a DLDO and reduces the gain to the minimum value to obtain a stable output voltage. Moreover, a novel uni-directional barrel shifter is proposed to reduce the aging effect of the DLDO. This uni-directional barrel shifter evenly distributes the load among DLDO output stages to obtain a longer lifetime. The benefits of the proposed techniques are explored and highlighted through extensive simulations. The proposed techniques also have negligible power and area overhead. NBTI-aware design with AGS can reduce the transient response time by 59.5% as compared to aging unaware conventional DLDO and can mitigate the aging effect up to 33%.

With the advent of on-chip digital low-dropout (DLDO) regulators, distributed on-chip voltage regulation has become increasingly promising. Environmental and operating conditions have been demonstrated to degrade DLDO performance, which directly affects execution accuracy. The area overhead (OH) needed to compensate aging-induced voltage noise degradation can be significant. Accordingly, in this paper, the algorithmic noise tolerance of certain processor components is exploited as an area-quality control knob to trade the program output quality for area OH. Furthermore, efficient and lightweight techniques utilizing a unidirectional shift register and reduced clock pulsewidth triggering are proposed to realize a novel aging-aware (AA) DLDO to achieve a better area and quality tradeoff. Owing to the large number and distributed nature of voltage regulators, with the proposed design, both the number of regulators utilized in the system and the size of each local regulator are scalable to satisfy the needs of different applications and processor components with varying algorithmic noise tolerance. It is demonstrated through simulation of an IBM POWER8 like processor that the proposed AA design can achieve up to, respectively, 43.2% and 3x transient and steady-state performance improvement. Additionally, more than 10% area OH saving can be achieved over a 5-year period.

On-chip digital low-dropout voltage regulators (LDOs) have recently gained impetus and drawn significant attention for integration within both mobile devices and micro-processors. Although the benefits of easy integration and fast response speed surpass analog LDOs and other voltage regulator types, NBTI induced performance degradation is typically overlooked. The conventional bi-directional shift register based controller can even exacerbate the degradation, which has been demonstrated theoretically and through practical applications. In this paper, a novel uni-directional shift register is proposed to evenly distribute the electrical stress and mitigate the NBTI effects under arbitrary load conditions with nearly no extra power and area overhead. The benefits of the proposed design as well as reliability aware design considerations are explored and highlighted through simulation of an IBM POWER8 like processor under several benchmark applications. It is demonstrated that the proposed NBTI-aware design can achieve up to 43.2% performance improvement as compared to a conventional one.

As an essential part of modern power delivery networks, on-chip voltage regulation consisting of multiple distributed voltage regulators provides the required power and voltage levels for localized load circuits. The harsh application environment of internet of things (IoT) and heterogeneous computing systems including, but not limited to, high temperature and large load current variations, can lead to significant and uneven performance degradations of on-chip voltage regulators due to aging. Investigating sustainable on-chip voltage regulation schemes considering the lifetime of different distributed voltage regulators becomes imperative. Furthermore, techniques to mitigate the aging induced voltage regulator degradations can consume the scarce on-chip area resource. In this work, a new reliable on-chip voltage regulation technique is explored to simultaneously mitigate the performance degradation and reduce the area cost of distributed on-chip voltage regulators to achieve sustainable and compact design and satisfy the needs of different IoT and heterogeneous computing systems considering the interactions among different regulators. A brief survey of reliable design challenges and potential solutions is also provided.

A duty cycle controlled pulse width modulator (PWM) is designed and tailored to provide PVT (process, voltage and temperature) stable, duty cycle comparison based PUF primitive for security applications. The proposed circuit uses a current starved ring oscillator whose duty cycle can be controlled over a wide range of 20%-90%. This proposed PVT compensated circuit provides a stable and uniform duty cycle with a worst case error between 1%-2% over an operating temperature range of 0°C-100°C, supply voltage range of 0.95 V-1.05 V, and fast fast (FF) and slow slow (SS) manufacturing process conditions. This proposed reliable and controlled PUF primitive is configurable to accept controlled random digital inputs to provide random and configurable duty cycle output values over a wide range.

Parallel on-chip voltage regulation, where multiple regulators are connected to the same power grid, has recently attracted significant attention with the proliferation of small on-chip voltage regulators. In this article, the number, size, and location of parallel low-dropout (LDO) regulators and intentional decoupling capacitors are optimized using mixed integer non-linear programming formulation. The proposed optimization function concurrently considers multiple objectives such as area, power noise, and overall power consumption. Certain objectives are optimized by putting constraints on the other objectives with the proposed technique. Additional constraints have been added to avoid the overlap of LDOs and decoupling capacitors in the optimization process. The results of an optimized LDO allocation in the POWER8 chip is compared with the recent LDO allocation in the same IBM chip in a case study where a 20% reduction in the noise is achieved. The results of the proposed multi-criteria objective function under a different area, power, and noise constraints are also evaluated with a sample ISPD’11 benchmark circuits in another case study.

The emergence of internet of things (IoT) devices is challenging the conventional design targets for integrated systems such as performance, power efficiency, and cost. With the proliferation of IoT devices, ensuring safe operating margins will become more crucial due to the limited power budget and physical constraints. Additionally, IoT devices are vulnerable to hardware attacks as they may be easily accessible to an attacker. The limitations when combined with the cost constraints make the design of security measures for the IoT devices quite challenging. In this perspective paper, reconfigurable voltage regulators are investigated to simultaneously improve the overall power efficiency of the system and provide enhanced security against certain side-channel attacks. A brief survey of randomized reconfiguration of voltage regulators to scramble to power consumption profile is proposed. The randomized reconfiguration makes the the synchronization of the attack more difficult for the attacker, boosting the security benefits of conventional voltage regulators with negligible power and area overhead.

EM side-channel leakage is typically the derivative of the power consumption profile of a circuit. Since the fluctuations of the supply voltage strongly depend on the topology and characteristics of the power distribution network (PDN), the design of the PDN has a direct impact on the EM side-channel leakage signature. In this paper, the security implications of distributed on-chip voltage regulators against EM side-channel attacks are investigated. Extensive HFSS simulations have demonstrated that the maximum EM radiation can be reduced by 33 dB and 11 dB, respectively, at the front and back sides of an integrated circuit with distributed on-chip voltage regulation since the power is delivered locally through partially shorter and thinner metal lines as compared to the designs with offchip voltage regulators.

Tailoring the operating voltage to fine-grain temporal changes in the power and performance needs of the workload can effectively enhance power efficiency. Therefore, power-limited computing platforms of today widely deploy integrated (i.e., on-chip) voltage regulation which enables fast fine-grain voltage control. Voltage regulators convert and distribute power from an external energy source to the processor. Unfortunately, power conversion loss is inevitable and projected integrated regulator designs are unlikely to eliminate this loss even asymptotically. Reconfigurable power delivery by selective shut-down, i.e., gating, of distributed on-chip regulators in response to spatio-temporal changes in power demand can sustain operation at the minimum conversion loss. However, even the minimum conversion loss is sizable, and as conversion loss gets dissipated as heat, on-chip regulators can easily cause thermal emergencies due to their small footprint.

In this paper, the security implications of the noise insertion characteristics of different countermeasures against power analysis attacks are investigated. Through optimizing the selection of the type and sequence of the inserted noise, the security of a cryptographic circuit that has multiple countermeasures with varying noise insertion mechanisms can be improved. As demonstrated in this work, if the additive non-white noise and multiplicative noise are sequentially inserted into a cryptographic circuit, the correlation coefficient between the actual power dissipation of the cryptographic circuit and monitored power dissipation can be reduced over 37.6% under the same amount of inserted noise.

Using minimum, even insufficient guards are proposed to achieve the spectral efficiency and latency requirements of cellular communication systems beyond 5G. This leads to interference in both time and frequency domains. In this paper, a partial-non-orthogonal multiple accessing scenario in which the desired user is experiencing both intersymbol interference (ISI) due to insufficient cyclic prefix (CP) and adjacent channel interference (ACI) caused by asynchronous transmitters using non-orthogonal numerologies in adjacent bands is investigated. ISI and ACI depend on the power offset between desired and interfering users, the instantaneous channel impulse responses of interfering users and transmitter and receiver window functions. Therefore, joint and adaptive utilization of CP requires real-time calculation of ISI and ACI. Analytical expressions for expected ISI and ACI at each subcarrier of the desired user are derived to minimize their combination. Accordingly, an adaptive algorithm consisting of windowing each subcarrier at the receiver with window length that minimizes the combined interference at that subcarrier by optimally exchanging ISI and ACI is proposed. Interference reduction performances of current, outdated and average optimal window length raised cosine receiver windows are assessed and compared to fixed and no receiver windowing. Windowing reduces interference even when CP is shorter than the channel if window length is determined using the proposed design guidelines.

A false key-controlled aggressive voltage scaling (AVS) technique is proposed as a countermeasure against leakage power analysis (LPA) attacks. A random number of false keys are utilized to control the supply voltage scaling to mask the possible leakage of the information related to the correct key to a malicious attacker. Contrary to the random AVS technique, false key-controlled AVS technique can guarantee that the added false keys always exhibit higher correlation coefficients than that of the correct key even if sufficient number of plaintexts (>10 million) are enabled. As demonstrated with the simulation results, the measurement-to-disclose (MTD) value of a cryptographic circuit can be enhanced over ten million against LPA attacks by utilizing the proposed technique, while the MTD values of a conventional cryptographic circuit without countermeasure and one with random AVS are, respectively, less than 500 and 100,000.

Power delivery networks with distributed on-chip voltage regulators (VRs) serve as an effective way for fast localized voltage regulation within modern microprocessors. Without careful consideration of the interactions among the distributed VRs and the power grid, unbalanced current sharing (CS) among those regulators may, however, lead to efficiency degradations, stability, and reliability issues, and even malfunctions of the regulators. This paper is a first attempt to investigate the efficiency, stability, and reliability implications of unbalanced CS among distributed on-chip VRs. Benefits of balanced CS are demonstrated with concrete examples, showing the necessity of an appropriate current balancing scheme. An adaptive reference voltage control method and the corresponding control algorithms specifically for distributed on-chip VRs are proposed to balance the CS among regulators at different locations. The proposed techniques successfully balance the CS among distributed VRs and can be applied to different regulator types. Simulation results based on practical microprocessor setups confirm the efficiency, stability, and reliability implications.

A voltage converter with adaptive security features is proposed as a lightweight countermeasure against leakage power analysis (LPA) attacks. When an LPA attack is sensed by the proposed security-adaptive (SA) voltage converter, a discharging resistor starts sinking redundant current to alter the signature of the load power dissipation. The power dissipation induced by the discharging resistor is scrambled by the SA voltage converter to maximize the amount of the inserted noise to the input power profile of the cryptographic against LPA attacks. As compared with a conventional cryptographic circuit that does not house any countermeasure, the lowest measurement-to-disclose value of a cryptographic circuit that employs the proposed voltage converter can be enhanced over 6145 times against LPA attacks.

While the wireless communication systems provide the means of connectivity nearly everywhere and all the time, communication security requires more attention. Even though current efforts provide solutions to specific problems under given circumstances, these methods are neither adaptive nor flexible enough to provide security under the dynamic conditions which make the security breaches an important concern. In this paper, a cognitive security (CS) concept for wireless communication systems in the physical layer is proposed with the aim of providing a comprehensive solution to wireless security problems. The proposed method will enable the comprehensive security to ensure a robust and reliable communication in the existence of adversaries by providing adaptive security solutions in the communication systems by exploiting the physical layer security from different perspective. The adaptiveness relies on the fact that radio adapts its propagation characteristics to satisfy secure communication based on specific conditions which are given as user density, application specific adaptation, and location within CS concept. Thus, instead of providing any type of new security mechanism, it is proposed that radio can take the necessary precautions based on these conditions before the attacks occur. Various access scenarios are investigated to enable the CS while considering these conditions.

Side-channel attacks have become a significant threat to the integrated circuit security. Circuit level techniques are proposed in this paper as a countermeasure against side-channel attacks. A distributed on-chip power delivery system consisting of multi-level switched capacitor (SC) voltage converters is proposed where the individual interleaved stages are turned on and turned off either based on the workload information or pseudo-randomly to scramble the power consumption profile. In the case that the changes in the workload demand do not trigger the power delivery system to turn on or off individual stages, the active stages are reshuffled with so called converter-reshuffling to insert random spikes in the power consumption profile. An entropy based metric is developed to evaluate the security-performance of the proposed converter-reshuffling technique as compared to three other existing on-chip power delivery schemes. The increase in the power trace entropy with CoRe scheme is also demonstrated with simulation results to further verify the theoretical analysis.

The primary objective of this paper is to investigate and evaluate the thermal implications of high power density on-chip voltage regulators. This paper is a first attempt to highlight the importance of the number, size, and location of on-chip voltage regulators on the thermal hotspots and thermal gradient. The physical location of on-chip voltage regulators is explored to distribute the hotspot locations and achieve spatial low pass filtering of the hotspots. A new thermal-aware physical design and power management technique are proposed to spatially and temporally distribute the hotspot locations over the cooler areas within an integrated circuit. The proposed technique eliminates the thermal gradient due to on-chip voltage regulators without any performance loss.

Design-for-power has become one of the primary objectives with the continuous demand to improve the battery life of mobile devices or minimize the cooling costs of servers. To save power and mitigate thermal emergencies, circuits typically enter reduced power states when the workload is light. Voltage regulators, however, operate indifferently under varying workload conditions due to the lack of different operating modes. When a voltage regulator is optimized for a particular load current, significant power is dissipated during voltage conversion while delivering a different load current. Adaptive activity management of on-chip voltage regulators based upon the workload information is exploited in this paper to force each on-chip regulator to operate in its most power-efficient load current. In the proposed regulator-gating (ReGa) technique, regulators are adaptively turned on (off) when the current demand is high (low) to improve the voltage conversion efficiency. With the proposed ReGa technique, the overall voltage conversion efficiency from the battery or off-chip power supply to the output of on-chip voltage regulators is improved ~3x.

A digitally controlled pulse width modulator (PWM), targeting on-chip power management applications is proposed in this paper. A current starved ring oscillator, with digitally controlled current source based headers and footers, is used to provide a versatile duty cycle and an accurate frequency control. The proposed circuit achieves i) a controlled duty cycle that can vary between 20% and 90% and ii) a compensation circuit that guarantees a constant duty cycle under process, voltage, and temperature (PVT) variations. A fast response time of 5 ns - 20 ns with a fine duty cycle granularity has been achieved through the proposed control techniques. The circuit operates at a frequency range of 500 MHz - 1.66 GHz and is implemented with a 22 nm CMOS predictive technology model.

A digitally controlled current starved pulse width modulator (PWM) is described in this paper. The current from the power grid to the ring oscillator is controlled by a header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, permitting the duty cycle to vary between 25% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. A ring oscillator with two header circuits is proposed to control both duty cycle and frequency of the operation. Analytic closed-form expressions for the operation of a PWM are provided. The accuracy and performance of the proposed PWM is evaluated with 22-nm CMOS predictive technology models under PVT variations. An error of less than 3.1% and 4.4% in the duty cycle, respectively, with and without constant frequency control is reported for the PWM. A constant operation frequency with less than 1.25% period variation is demonstrated. The proposed PWM is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under PVT variations.

A methodology is proposed to determine the current profile early in the design process to accurately estimate electromagnetic emissions. Design information describing the clock and power distribution network topologies and the placement and sizing of the decoupling capacitors is used to determine the current signatures of individual circuit blocks and the entire system. The proposed methodology is incorporated within the integrated circuit emission model (ICEM). Current profiles for various circuits with different characteristics are determined using the proposed model.

A digitally controlled current starved pulse width modulator is described in this paper. The current from the power grid to the ring oscillator is controlled by a header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, permitting the duty cycle to vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The accuracy and performance of the proposed digitally controlled pulse width modulator is evaluated with 22 nm CMOS predictive technology models under PVT variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations. Although the frequency of the switching signal is affected by changes in the duty cycle, the frequency variations are typically negligible.

An active filter-based on-chip DC-DC voltage converter for application to distributed on-chip power supplies in multivoltage systems is described in this paper. No inductor or output capacitor is required in the proposed converter. The area of the voltage converter is therefore significantly less than that of a conventional low-dropout (LDO) regulator. Hence, the proposed circuit is appropriate for point-of-load voltage regulation for noise sensitive portions of an integrated circuit. The performance of the circuit has been verified with Cadence Spectre simulations and fabricated with a commercial 110 nm complimentary metal oxide semiconductor (CMOS) technology. The area of the voltage regulator is 0.015 mm2and delivers up to 80 mA of output current. The transient response with no output capacitor ranges from 72 to 192 ns. The parameter sensitivity of the active filter is also described. The advantages and disadvantages of the active filter-based, conventional switching, linear, and switched capacitor voltage converters are compared. The proposed circuit is an alternative to classical LDO voltage regulators, providing a means for distributing multiple local power supplies across an integrated circuit while maintaining high current efficiency and fast response time within a small area.

Closed form expressions and related algorithms for fast power grid analysis are proposed in this paper. The IR voltage drop at an arbitrary point in a power distribution network is determined. Two algorithms are described for non-uniform voltage supplies and non-uniform current loads distributed throughout a power grid. The principle of spatial locality is exploited to accelerate the proposed power grid analysis method. Analysis of the non-uniform power grids utilizes the principle of spatial locality. Since no iterations are required for the proposed IR drop analysis, the proposed algorithms are over 70 times faster for smaller power grids composed of less than five million nodes and over 180 times faster for larger power grids composed of more than 25 million nodes as compared to existing methods. The proposed method exhibits less than 0.5% error.

Design guidelines for shielding in the presence of power/ground (P/G) noise are presented in this paper. The effect of P/G noise on crosstalk is analyzed for different line lengths, line widths, and interconnect driver resistances. Considering the P/G noise, a shield line can degrade rather than enhance signal integrity due to increased P/G noise coupling on the victim line. A$2\pi$RLC interconnect model is used to investigate the effects of both coupling capacitance and mutual inductance on the crosstalk noise. Physical spacing and shield insertion are compared in terms of the coupling noise on the victim line for several technology nodes. Boundary conditions are also provided to determine the effective range of spacing and shield insertion in the presence of P/G noise. Additionally, the effects of technology scaling on P/G noise and shielding efficiency are discussed, and related design tradeoffs are addressed.

An ultra-low area, current efficient voltage regulator appropriate for distributed point-of-load voltage regulation in high performance integrated circuits (ICs) is described in this paper. The proposed voltage regulator is a hybrid combination of a switching voltage regulator and a linear voltage regulator. The voltage regulator can supply over 100 mA current while generating 0.9 volts from a 1.2 input voltage. The current efficiency exceeds 99% while the load regulation to a step current ranges between 40 ns and 60 ns. No output capacitor is required to ensure stability. Hence, the required on-chip area is as small as 0.026 mm^2 for the proposed voltage regulator which is approximately four to six times smaller than area efficient low dropout regulators. The proposed circuit therefore provides a means for distributing multiple local power supplies across an integrated circuit, maintaining high current efficiency and small area.

A hybrid voltage regulator module for an on-chip DC-DC voltage converter is proposed in this paper. The circuit is appropriate for point-of-load voltage regulation due to an ultra area efficient architecture. The proposed voltage regulator is a hybrid combination of a switching DC-DC voltage converter and a low-dropout regulator exploiting active circuitry rather than bulky passive devices within the filter structure. The proposed circuit can supply over 100 mA current while generating 0.9 volts from a 1.2 input voltage, exhibiting a high current efficiency of greater than 99%. The on-chip area is 0.026 mm2which is 500 times smaller than a monolithic buck converter and four times smaller than an LDO. The proposed regulator provides a means for distributing multiple local power supplies across an integrated circuit while providing high current efficiency.

The size of on-chip power distribution networks is increasing with each technology generation. Accurate and computationally efficient analysis of these power distribution networks has therefore become increasingly challenging. High performance power distribution networks are generally implemented as a uniform mesh structure. The uniformity of these power distribution networks can be exploited for fast, accurate nodal analysis. A closed form expression is presented here for determining the voltage at any arbitrary node in a power distribution network. The error of the proposed method as compared with SPICE is less than 0.2%. Since no iterations are required, the proposed method significantly outperforms previously proposed power grid analysis techniques in terms of computational speed while exhibiting low error.

Design guidelines for shielding in the presence of power/ground (P/G) noise are presented in this paper. The effect of noise in the P/G network is analyzed for various line lengths, line widths, and interconnect driver resistances. A 2pi RLC model is used to investigate the effect of both coupling capacitance and mutual inductance on the crosstalk noise. For a range of shield lengths and widths, a shield line can degrade signal integrity by increasing the crosstalk noise on the victim line. Different physical spacing and shield insertion methods are compared for various parameters in terms of the coupling noise on the victim line for a 65 nm technology node.