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Charlotte Y. Lau

dblp:89/382 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 87% Electronic design automation · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits		 0.012003
Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm · DAC 2003
Integrated circuit design › analog and mixed-signal circuits › mixed-signal circuit design
phase-locked loop		 0.012003
Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm · DAC 2003
Electronic design automation
analog circuit synthesis		 0.012003
Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm · DAC 2003

Methods — techniques the papers use, named apart from their topics

transfer function analysis · 0.0closed-loop realization algorithm · 0.0
YearPublicationVenuePosition
2003 Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm
abstract
A new methodology for designing fractional-N frequency synthesizers and other phase locked loop (PLL) circuits is presented. The approach achieves direct realization of the desired closed loop PLL transfer function given a set of user-specified parameters and automatically calculates the corresponding open loop PLL parameters. The algorithm also accomodates nonidealities such as parasitic poles and zeros. The entire methodology has been implemented in a GUI-based software package, which is used to verify the approach through comparison of the calculated and simulated dynamic and noise performance of a third order fractional-N frequency synthesizer.
Charlotte Y. Lau, Michael H. Perrott
 DAC1