Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Clement Luk

dblp:89/4339 · DBLP profile ↗
← Back
5ranked-venue papers
1as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 99% Processor architecture and microarchitecture · 1% Integrated circuit design · 0%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation
0.012003
INDUCTWISE: inductance-wise interconnect simulator and extractor · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003
Electronic design automation › interconnect modeling
inductance extraction
0.012003
INDUCTWISE: inductance-wise interconnect simulator and extractor · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003
Electronic design automation
interconnect modeling
0.012003
INDUCTWISE: inductance-wise interconnect simulator and extractor · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003
Electronic design automation › circuit simulation
transient analysis
0.012003
INDUCTWISE: inductance-wise interconnect simulator and extractor · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003
Processor architecture and microarchitecture
instruction set architecture
0.011975
Algorithms for Binary Coded Balanced and Ordinary Ternary Operations · IEEE Trans. Computers 1975
Processor architecture and microarchitecture › computer arithmetic
ternary arithmetic
0.011975
Algorithms for Binary Coded Balanced and Ordinary Ternary Operations · IEEE Trans. Computers 1975
Integrated circuit design
digital circuit design
0.011975
Algorithms for Binary Coded Balanced and Ordinary Ternary Operations · IEEE Trans. Computers 1975

Methods — techniques the papers use, named apart from their topics

nodal analysis · 0.0matrix sparsification · 0.0ternary subtraction algorithm · 0.0ternary addition algorithm · 0.0
YearPublicationVenuePosition
2004 Frequency-dependent reluctance extraction
Clement Luk, Tsung-Hao Chen, Charlie Chung-Ping Chen
ASP-DAC1
2003 SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation
Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen
ICCAD2
2003 INDUCTWISE: inductance-wise interconnect simulator and extractor
abstract
A robust, efficient, and accurate inductance extraction and simulation tool, INDUCTWISE, is developed and described in this paper. This work advances the state-of-the-art inductance extraction and simulation techniques, and has several major contributions. First, albeit the great benefits of efficiency, the recently proposed inductance matrix sparsification algorithm, the-method (Ji et al. 2001), has a flaw in the stability proof for general geometry. We provide a theoretical analysis as well as a provable stable algorithm for it. Second, a robust window-selection algorithm is presented for general geometry. Third, integrated with the nodal analysis formulation, INDUCTWISE achieves exceptional performance without frequency-dependent complex operations and directly gives time-domain responses. Experimental results show that INDUCTWISE extractor and simulator have dramatic speedup compared to FastHenry and SPICE3, respectively. It has been well tested and released on the web for public usage (Available: http://vlsi.ece.wisc.edu/Inductwise.htm).
Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2002 INDUCTWISE: inductance-wise interconnect simulator and extractor
abstract
We develop a robust, efficient, and accurate tool, which integrates inductance extraction and simulation, called INDUCTWISE. This paper advances the state-of-the-art inductance extraction and simulation techniques and contains two major parts. In the first part, INDUCTWISE extractor, we discover the recently proposed inductance matrix sparsification algorithm, the K-method[1], albeit its great benefits of efficiency, has a major flaw on the stability. We provide both a counter example and a remedy for it. A window section algorithm is also presented to preserve the accuracy of the sparsification method. The second part, INDUCTWISE simulator, demonstrates great efficiency of integrating the nodal analysis formulation with the improved K-method. Experimental results show that INDUCTWISE has over 250x speedup compared to SPICE3. The proposed sparsification algorithm accelerates the simulator another 175x and speeds up the extractor 23.4x within 0.1% of error. INDUCTWISE can extract and simulate an 118K-conductor RKC circuit within 18 minutes. It has been well tested and released on the web for public usage. (http://vlsi.ece.wisc.edu/Inductwise.htm)
Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, Charlie Chung-Ping Chen
ICCAD2
1975 Algorithms for Binary Coded Balanced and Ordinary Ternary Operations
abstract
A representation for binary coded ternary (BCT) numbers is proposed. This representation is then used for the introduction of algorithms for ternary addition and subtraction on binary hardware. In the algorithm introduced, distinction is made between basic algorithms, i.e., those which are independent of the type of the arithmetic, and those which are dependent upon it. Some suggestions as to the significance of this approach for nonternary arithmetic are presented.
Gideon Frieder, Clement Luk
IEEE Trans. Computers2