In a context of high performance, low technology access cost and application code reusability objectives, this paper presents an "architectured FPGA" approach that consists in the definition of a general frame for embedded system application implementations. Addressing image processing as a first application domain, a FPGA architecture implementation based on that approach is presented. Built around SIMD architecture, the "Ter@Core" FPGA implementation illustrates the competitiveness of the approach compared to off-the-shelf processors and to usual FPGA approach. The presented implementation gathers 128 processing elements on a single FPGA providing 19.2 GOPS performance and very high application development productivity.

A parallel MIMD type processor for use in image processing applications on board satellites is described. Emphasis is given to the application requirements in terms of processing power, type of parallelism, communication need and to the impact of these requirements on the architecture design. The choice of a MIMD processor with a ring bus, the convenience of a multiple bus structure, the definition of the bus protocole, the synchronization mechanism and the typical performances are presented as successive choices and discussed in regard of the requirements. Possibilities and limits of the architecture are carefully analyzed: Typical examples of efficiently implementable applications in other fields of image processing are given. But limits of the structure are pointed out for other types of parallel processing.