Due to commercial pressures, North-American printed circuit-board assembly manufacturers have had to reposition themselves in the more difficult market segment of lower volume, higher complexity products, also called high-mix, low-volume (HMLV). The high per-unit costs of these products justify substantial diagnosis and repair efforts when defects are detected in production. Although automated diagnostics is desirable, the low production volumes impose severe limits on available data. We propose a novel approach based on knowledge modeling and case-based reasoning for automated diagnosis of assembled printed circuit boards in an HMLV production environment. Our hybrid approach can overcome the knowledge-acquisition bottleneck even in a data-poor environment. The proposed approach does not require contributions from product designers or experts and is designed to operate using only information available during manufacturing. Our test results show that our diagnostic system can detect, locate and classify all single faults and multiple faults affecting up to three neighboring nodes with a better success rate than the reference commercial tool. Moreover, case base data, including board layout information and user feedback from previous repairs, is used to feed a recommender system to provide repair suggestions. A production and repair data simulator is described and used to evaluate the recommender system’s effectiveness.

Classical transition delay fault (TDF) model-based delay tests cannot detect small-delay defects (SDDs) properly in many circuits because they do not set the test slack properly to match the size of the tested delay fault. In this article, we propose a new method of using faster-than-at-speed clocks to enhance a classical TDF-based test pattern set and create an optimized SDD test that can detect effective SDDs. We define effective SDDs as SDDs that can immediately fail a circuit and distinguish them from those that grow over time to fail the circuit (reliability defects). The optimized SDD test developed in this article can either target only effective SDDs or also include reliability defects that are close to fail a circuit. In order to improve the SDD test quality, the proposed optimization method uses the recently proposed weighted slack percentage (WeSPer) as the SDD test quality metric to match each pattern with an appropriate test clock speed and then generates the proper masking vector. The optimization method includes a technique for reducing the final pattern count while keeping WeSPer value high. On a set of benchmark circuits, the proposed technique is able to improve the WeSPer value by up to 32.97% (a relative improvement of 60.98%) compared to classical at-speed testing using the same pattern set. This article also discusses the application of this technique on a self-timed circuit that has previously been at-speed tested. The proposed optimization technique improved the SDD test quality from 60% to 69% for preexisting set of test clocks and patterns. Post-silicon test results for the processor are included in this article.

This paper explores the use of dynamic voltage scaling (DVS) for a particular type of asynchronous circuits, namely the single-rail bundled-data handshake-free asynchronous circuits. With respect to their synchronous counterparts, applying DVS to the targeted type of circuits imposes additional timing constraints that must be met to ensure correct operation. A new model defining these additional constraints is proposed. Such DVS related constraints were never explicitly formulated. The proposed model considers setup and hold timing constraints and transition degradation to ensure proper timing closure. Reported simulation results show that the timing constraints can be satisfied while applying DVS, but also that adjustments might be required to ensure proper pulse propagation and efficient operations.

The application of scan-based at-speed delay testing on asynchronous circuits is not trivial. Their unorthodox design leaves them generally incompatible with traditional synchronous design and test tools, as well as standard automatic test equipment. The correct generation of at-speed test clocks and the use of conventional automatic test patterns generation (ATPG) tools are some of the problems that face the application of at-speed testing on asynchronous circuits. This paper presents a method of applying scan-based at-speed testing on single-rail bundleddata handshake-free (self-timed) asynchronous circuits by taking advantage of built-in delay lines. The proposed test method uses launch-on-capture scan-based testing with endpoint masking and generates the test patterns using conventional ATPG tools. The proposed test is applied on circuits in a self-timed microprocessor fabricated in 28nm FD-SOI CMOS technology. This method is validated by the reported test coverage and simulation results, along with post-silicon test results on a Teradyne FLEX tester.

This paper presents a new scan-based at-speed test signal scheme called One Clock Alternated Shift (OCAS) for minimizing the potential impact of the power distribution network PDN impedance variation. The strategy behind this new scheme is to mimic the clock signal of the functional mode as closely as possible. As a case study, we consider the PDN impedance variation that can occur with 3-D ICs, more specifically when a top die under test is bounded over a stack of different sizes. HSpice simulation results show that OCAS is less sensitive to such impedance variation when compared to existing scan-based at-speed testing techniques, mainly, SeBoS, and BurstMode.

Successive-cancellation list (SCL) decoding is an algorithm that provides very good error-correction performance for polar codes. However, its hardware implementation requires a large amount of memory, mainly to store intermediate results. In this paper, a partitioned SCL algorithm is proposed to reduce the large memory requirements of the conventional SCL algorithm. The decoder tree is broken into partitions that are decoded separately. We show that with careful selection of list sizes and number of partitions, the proposed algorithm can outperform conventional SCL while requiring less memory.

This paper describes a practical design method for protoyping self-timed processors using FPGAs. It adresses shortcomings of typical implementation strategies that use floorplanning to compensate for the lack of support of asynchronous designs in conventional FPGA tools. It is shown that a reported self-timed design technique can be used with a proposed set of constraints to make it fully compliant with standard timing analysis engines. This results in a more effective implementation strategy that makes FPGAs convenient for verifiying self-timed processor designs. The design technique and the timing-driven implementation method are validated by protoyping an 8-bit processor that achieves 11.1 MIPS performance while computing the Fibonacci sequence.

Polar codes are an exciting new class of error correcting codes that achieve the symmetric capacity of memoryless channels. Many decoding algorithms were developed and implemented, addressing various application requirements: from error-correction performance rivaling that of LDPC codes to very high throughput or low-complexity decoders. In this work, we review the state of the art in polar decoders implementing the successive-cancellation, belief propagation, and list decoding algorithms, illustrating their advantages.

Testing for small delay defects (SDDs) is important due to their dominance in recent technology nodes. Unfortunately, all the SDD test quality metrics in the literature limit their assessment to the size of the delay defect tested under at-speed or slower clocks, which makes their results misleading under special cases such as faster-than-at-speed testing. Moreover, those metrics are inadequate for assessing the quality of recent SDD test methods that consider the variation of delays in a circuit. In this paper, a novel flexible SDD quality metric that can be adapted according to the available information and the applied test method is proposed. The proposed metric is named Weighted Slack Percentage (WeSPer) as it is defined by a slack ratio weighted by confidence level (CL) multipliers. The flexibility comes from the ability to model test inaccuracies or delay varying effects into the CL multipliers. This paper presents the WeSPer metric, along with a CL multiplier that penalizes overtesting to give a more accurate assessment of the quality of faster-than-at-speed testing. The metric is calculated for several benchmark circuits and compared to other SDD metrics found in the literature. The results show that WeSPer is better than other metrics at representing the quality of SDD tests, especially under faster-than-at-speed testing.

Polar codes asymptotically achieve the symmetric capacity of memoryless channels, yet their error-correcting performance under successive-cancellation (SC) decoding for short and moderate length codes is worse than that of other modern codes such as low-density parity-check (LDPC) codes. Of the many methods to improve the error-correction performance of polar codes, list decoding yields the best results, especially when the polar code is concatenated with a cyclic redundancy check (CRC). List decoding involves exploring several decoding paths with SC decoding, and therefore tends to be slower than SC decoding itself, by an order of magnitude in practical implementations. In this paper, we present a new algorithm based on unrolling the decoding tree of the code that improves the speed of list decoding by an order of magnitude when implemented in software. Furthermore, we show that for software-defined radio applications, our proposed algorithm is faster than the fastest software implementations of LDPC decoders in the literature while offering comparable error-correction performance at similar or shorter code lengths.

In this paper, we present hardware and software implementations of flexible polar systematic encoders and decoders. The proposed implementations operate on polar codes of any length less than a maximum and of any rate. We describe the low-complexity, highly parallel, and flexible systematic-encoding algorithm that we use and prove its correctness. Our hardware implementation results show that the overhead of adding code rate and length flexibility is little, and the impact on operation latency minor compared with code-specific versions. Finally, the flexible software encoder and decoder implementations are also shown to be able to maintain high throughput and low latency.

This paper presents a new and highly efficient approach for the estimation by fault injection of the sensitivity to Single Event Upsets of circuits implemented in Xilinx SRAM-based FPGAs. The proposed approach prioritizes fault injection in specific configuration bits subsets defined according to their contents and the type of FPGA resources that they are configuring. The new approach also allows maximizing either the number of critical bits flipped during the injection or the estimation accuracy of the critical bits number. The results show that the new approach outperforms the traditional random fault injection with speed up factors up to two orders of magnitude.

Welcome to VTS 2015, the thirty third in a series of annual symposia that focus on innovation in the field of testing of integrated circuits and systems.

The use of scan test patterns, generated at the gate level with automatic test pattern generation (ATPG) tools in design simulation, was proposed in our previous work to improve verification quality. A drawback of this method is the potential presence of illegal (or unreachable) states (ISEs) causing unwanted behavior and false error detection in the verification process. In this brief, we present a new automated tool that helps overcome this problem. The tool extracts functional constraints at the register transfer level on a VHDL description (it can be easily adapted to any other hardware description language). The constraints extracted are used in the ATPG process to generate pseudofunctional scan test patterns which avoid the ISEs. The whole verification environment incorporating the proposed tool is presented. Experimental results show the tool impact on the reduction of false error detection in verification. In addition, it shows the verification quality improvements with the proposed environment in terms of coverage, time, and complexity.

Among error-correcting codes, polar codes are the first to provably achieve channel capacity with an explicit construction. In this work, we present software implementations of a polar decoder that leverage the capabilities of modern general-purpose processors to achieve an information throughput in excess of 200 Mbps, a throughput well suited for software-defined-radio applications. We also show that, for a similar error-correction performance, the throughput of polar decoders both surpasses that of LDPC decoders targeting general-purpose processors and is competitive with that of state-of-the-art software LDPC decoders running on graphic processing units.

Whereas the use of FPGAs in aerospace applications is increasing, concerns about its sensitivity to radiations more particularly the single event upsets (SEU) in SRAM-based FPGA is enhanced as well. To ensure hardness assurance, radiation sensitivity should be estimated at different stages of the system development cycle. In this paper, we present a multi-abstraction level signature generation based on fault injection using fault simulation, fault emulation and radiation testing in order to build an accurate representation of the design faulty behavior. These signatures, which can be seen as high-level fault models, help the designer make decisions on the use (or not) of rad-hard components and the adequate mitigation technique very early in the design process. Results from the different types of signatures are compared. It first shows that the type of resources used to implement a module (e.g. multiplier) may influence its behavior when affected by an SEU. It also reveals that most of the faulty values observed during radiation testing appear in the simulation-based and emulation-based signatures, but that their frequency of occurrence can differ. Finally, limitations of some commercial tools to identify critical bits are investigated.

SRAM-based FPGAs are increasingly popular in the aerospace industry for their field programmability and low cost. However, they suffer from cosmic radiation induced Single Event Upsets (SEUs), commonly known as soft errors. In safety-critical applications, the dependability of the design is a prime concern since failures may have catastrophic consequences. An early analysis of dependability of such safety-critical applications will enable designers to develop a design that meets the high availability and reliability requirements of the DO-254 standard. This paper introduces a novel methodology based on probabilistic model checking, to analyze the dependability properties of safety-critical systems and to suggest required mitigation techniques, such as Triple Modular Redundancy (TMR) or TMR with less frequent scrubs for early design decisions. Starting from a high-level description of a system, a Markov model is constructed from the Control Data Flow Graph (CDFG) expressing the functionality and from failure/mitigation parameters for the targeted FPGAs. Such an exhaustive model captures all the failures and repairs possible in the system within the radiation environment. We present a case study on a benchmark circuit to illustrate the applicability of the proposed approach to demonstrate that a wide range of useful dependability properties can be analyzed using our proposed methodology.

Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. The adoption of polar codes however, has been hampered by the low throughput of their decoding algorithm. This work aims to increase the throughput of polar decoding hardware by an order of magnitude relative to successive-cancellation decoders and is more than 8 times faster than the current fastest polar decoder. We present an algorithm, architecture, and FPGA implementation of a flexible, gigabit-per-second polar decoder.

In this paper, a multi user Multi-Carrier Differential Chaos Shift Keying (MC-DCSK) modulation is presented. The system endeavors to provide a good trade-off between robustness, energy efficiency and high data rate, while still being simple. In this architecture of MC-DCSK system, for each user, chaotic reference sequence is transmitted over a predefined subcarrier frequency. Multiple modulated data streams are transmitted over the remaining subcarriers allocated for each user. This transmitter structure saves energy and increases the spectral efficiency of the conventional DCSK system.

In this paper, implementation of discrete-time chaotic generators widely used in digital communications is studied and evaluated. The study focuses on power consumption, resource usage, and maximum execution frequency of implementations for two common Field Programmable Gate Arrays (FPGAs). While the Bernoulli map ranks first in all three aspects, results show significant ranking differences among the other chaotic generators. Results were obtained by first implementing the chaotic generators in a high level register to transistor level description language and then using tools from FPGA manufacturers to obtain the resource usage as well as estimate the other desired characteristics.

Parasitic memory effect can occur due to the impact of parasitic node capacitances and faulty node voltages on the electrical behavior of SRAMs. This memory effect can cause detectable faults to become undetectable using existing industrial tests. This paper analyzes, evaluates and identifies the unique detection conditions for faults in SRAMs. It demonstrates the limitation of existing industrial tests that do not take the impact of parasitic memory effect into consideration. Finally, the paper presents March SME, a memory test that detects SRAM static faults in the presence of parasitic memory effect.

This paper presents a novel approach to extending the life of current-based test techniques for the detection and diagnosis of bridging defects. Called CΔIDDQ (Complementary ΔIDDQ), this approach combines a modified test pattern generation with a simple post-processing of IDDQmeasurements (namely additions and subtractions) such that the resulting measurement combination equals zero. Consequently, CΔIDDQ eliminates the main current variance sources: wafer-to-wafer, IC-to-IC and vector-to-vector variations; the only remaining source is the measurement variance. The modified test pattern generation is based on the innovative concept of transient-fault test pattern decomposition and the use of layout information to target realistic bridging defect sites. Verification based on logic simulation confirms that the combination of the resulting subset of fault-free IDDQmeasurements is equal to 0. Using this promising new technique, bridging defect detection capability can be improved by orders of magnitude. Simulation results also show that this improved detection capability may be necessary even for low-power devices.

This paper presents a novel approach to reject outliers based on parametric measurements, namely quiescent current and IC speed estimates. Unlike the existing multi-parameter or IDDQ-based techniques which use additional measurements to estimate the expected healthy IDDQresponse, the authors focus on the variance to reject outliers. The authors take advantage of the correlation between the two types of measurements and of the fact that speed estimate measurements are more reliable than leakage ones in order to evaluate the acceptable current variation level. For that, the authors derive approximate variance equations from basic current and delay equations. Using these variance equations, the authors are able to identify current variations that cannot be justified by normal process variations, based on simple outlier rejection criteria. This approach is developed to be used as a pre-processing tool to other post-processing techniques. Results are promising.

This paper proposes new current signatures for test purposes. It estimates their capabilities in the detection of additional current caused by weak resistive active and passive defects, when used separately and in combination with other current-based test techniques. Estimation results based in part on actual I/sub DDQ/ measurements show that current-based test technique combinations allow reliable detection of smaller current deltas and offsets. The extra margin provided by these combinations can also be used to reduce the yield losses associated to current-based test techniques by applying these test techniques more conservatively while keeping the same detection capabilities. The cost of adding a second set of I/sub DDQ/ test patterns can be greatly reduced if part of an adaptive test strategy.

The purpose of this paper is to introduce a new I/sub DDQ/ measurement technique based on active successive approximations, named ASA-I/sub DDQ/. This technique has unique features allowing to speed-up I/sub DDQ/ measurement. Experimental results suggests that a significant speed-up factor can be obtained over the QuiC-Mon technique.

A methodology to characterize thoroughly the defective behavior of CML bipolar gates has been developed. This methodology produced data suitable to guide design for testability in CML circuits. Inductive Fault Analysis (IFA) is first applied to library cell layouts to characterize their sensitivity to realistic defects. The data is then processed by an automatic simulation program that can, according to a list of criteria, classify the defective behavior of all cells. This complete analysis allows a thorough characterization of defective cell behaviors of such a logic family, and helps derive specific testability rules and methods. The proposed methodology is flexible enough to be adapted easily to other logic families.

This paper is part of our ongoing effort to replace I/sub DDQ/ testing. We analyze the effect of process drifting based on Sematech Project S121 data, and present a simple and efficient way to deal with these phenomena, when using a previously proposed test procedure based on Delta I/sub DDQ/ histograms. We also analyze the different variance sources in the same context. Following this analysis, we propose and validate an innovative strategy for test optimization based on the use of current test vectors (patterns) with a shorter settling time and on the concept of Delta I/sub DDQ/ partitioning. These new results and developments confirm the pertinence of our variance reduction strategy and reveal new possibilities in terms of test optimization targeting either a better test quality or a shorter current test time.

This paper presents an efficient method to diagnose single and double bridging faults. This method is based on Delta Iddq probabilistic signatures, as well as on the Viterbi algorithm, mainly used in telecommunications systems for error correction. The proposed method is a significant improvement over an existing one, based on maximum likelihood estimation. The (adapted) Viterbi algorithm takes into account useful information not considered previously. Simulation and experimental results are presented to validate the approach.

This paper proposes a very efficient method to diagnosis multiple bridging faults. This method is based on differential or Delta I/sub DDQ/ probabilistic signatures, as well as on the Viterbi algorithm, mainly used in telecommunications systems for error correction. The proposed method can be seen as a significant improvement over an existing one based on maximum likelihood estimation. The use of the (adapted) Viterbi algorithm allows us to take into account additional information not considered previously. The existing and the proposed method are first described. Then, simulation and experimental results are presented to validate the concept in the context of double faults. Bounds on false diagnosis probability are also provided, estimating the number of test/diagnosis vectors required to reach a given diagnosis reliability for a given number of gates. The bounds allow us to show that this probability exponentially decreases with the number of test vectors and that for, a given value of this probability, the number of vectors required is O(log2(G)), where G is the number of gates.

The purpose of this paper is to propose a new histogram-based differential current testing procedure of active defects. This procedure contains three steps: Preanalysis, Failure Analysis, and Production Testing. The main objectives of the Pre-analysis are to provide information on the most frequent active current defects and to help setting the limits between faulty and fault-free devices; these limits are then investigated during the Failure Analysis step in order to set the threshold between faulty and fault-free ICs. During the Production Testing step, this threshold is compared to the highest peak value appearing in a histogram built for each tested IC. Some selected results are presented, which confirm the test quality gain increase by using differential I/sub DDQ/ instead of I/sub DDQ/ itself as well as the additional reduction of bad test decision that can be obtained by a wise selection of test vectors reducing the vector-to-vector current variations.

The purpose of this paper is to compare differential Iddq to Iddq itself; in their capabilities of detecting active current defects/faults, as bridging faults. To perform this comparison, a mathematical framework is developed, based on assumptions validated with data from the Sematech experiment S121. The comparison results reveal that the probability of false test decision can be reduced by orders of magnitude by using differential Iddq instead of Iddq. Based on the same framework, we also show that a wise vector selection may contribute to decrease by orders of magnitude the probability of a false test decision. Finally, we investigate the applicability of differential Iddq with deep-submicron technologies, by estimating the number of (pairs of) vectors required to achieve a given test qualify level. The proposed framework and the results help to understand the tendencies and to identify the requirements in order to meet the challenges of deep-submicron current testing.

In this paper, a scan-based programmable, configurable, and scalable architecture is proposed. This architecture is suitable for a wide range of applications in signal processing requiring programmability and presenting high bandwidth and real-time requirements beyond the capacity of off-the-shelf DSPs or FGPAs. The architecture is specifically targeting a very common type of signal processing operation: sliding window operations (SWOs). Through various examples, the "programmability, configurability, and scalability" of the proposed architecture are illustrated. Our approach is then compared to traditional programmable architectures with coefficient registers in terms of gate count, speed (delay), and other implementation-related issues. This comparison reveals that our architecture leads to less complex solutions with comparable performance. In general, this approach can be seen as an alternative offering reduced recurrent costs at the expense of potentially higher nonrecurrent costs, which makes it very attractive for high volume production.

The purpose of this paper is to present experimental results validating a diagnosis method based on differential Iddq probabilistic signatures and on maximum likelihood estimation. First, SEMATECH Project S121 data is used to support assumptions about current behaviour. Then results obtained from an IC monitor containing controllable faults clearly show the capability of the method to identify the type of actual activated faults, in spite of a strong experimental current standard variation. These results validate previous simulation procedures, which are applied to estimate what can be expected with more common current standard variations.

In this paper, we propose a novel IC diagnosis approach, based on probabilistic differential quiescent current (I/sub DDQ/) signatures. Unlike the previous diagnosis approaches using current, this approach, using the maximum likelihood estimation, provides a solid framework allowing to quantify its robustness with respect to current measurement variations. The differential nature of the signatures allows to treat subthreshold leakage currents as a noise source. Results are provided showing the robustness of the approach. The applicability of the approach on embedded logic is also briefly discussed.

This paper presents the bases of a test method that can detect and locate faults and defects. This method is based on the use of digital signal processing applied on sampled current or voltage and can be applied to technologies with significant quiescent current. A simple procedure is also proposed in order to locate parasitic resistive contacts, and diagnosis potential of the method is explored.

In this paper, two equivalence proofs of yield modeling methods for defect-tolerant integrated circuits (ICs) are presented. These proofs are generalizations of those found in Koren and Stapper (1989); one of the proofs presented in this paper is valid for any defect-tolerant IC, while the other one is valid for defect-tolerant ICs with two levels of hierarchy.>

We present a method to accelerate the search for the number of spares to be included in defect tolerant integrated circuits. Our method is obtained by bringing two modifications to a conventional evaluation method. The main motivations behind the development of this method are: the possibilities offered by the implementation of defect tolerance, the existence of many yield models, which may predict different results in terms of optimum number of spares, and the fact that some models are very compute intensive. The modeling methods leading to several usual yield models are briefly presented. We also present results showing that our method is valid for a wide range of parameters. However, this method can be applied to all yield models considered and it can significantly reduce the time spent in the search for the best possible reconfiguration strategies.>