Reconnaissance is a crucial stage of cyberattacks, enabling attackers to gather information about system vulnerabilities.In computer networks, data regarding addressing and transmission paths is especially sensitive.This paper introduces a concept for a hybrid mutation system based on Software Defined Networking (SDN), combining address and data path mutation to improve security.The system employs central network management and pseudorandom, temporary addressing, which is periodically reconfigured.In contrast to existing Moving Target Defense (MTD) address mutation methods, end devices connect through dedicated agents, which can be implemented using a SmartNIC.The agent modifies packet headers at a network edge to obfuscate address information, minimizing the processing burden on SDN switches inside a network.The objective is to hinder attackers from discovering network details that could be exploited.A prototype was implemented using typical SDN components and containerized end devices.Tests confirmed the system's correctness and effectiveness in protecting the network structure and communication paths.This approach enhances the confidentiality of network parameters and limits the information available to potential attackers, making reconnaissance significantly more difficult, while minimizing SDN network control overhead.

The rapid growth of the Internet of Things has significant security implications.In the current IoT security landscape, many institutions and entities are defining security requirements, but no industry-wide standard has been agreed upon.There are solutions in the present state-of-the-art that fulfill a subset of secure IoT device requirements, but none adheres to all of them.However, the existing technologies introduced by those solutions could be combined to create a design framework which provides security baseline features to support requirements of a secure IoT device.In this paper, a configurable and comprehensive hardware-software security framework is proposed, that, when applied in the process of designing System on Chip for IoT, will ensure its cybersecurity by providing security core baseline features.The proposed sollution is CPU-agnostic, in the sense that no assumptions are made about the CPU's support for privilege levels, memory protection schemes, or any security mechanisms.

In this paper we present three virtualization devices (Xen server, NetFPGA and EZ appliance) which have been used for implementation of data plane functionality in a Future Internet architecture, the IIP System. We give general description of these devices and present implementation of the IIP System node on each device.

This paper presents a System on Programmable Chip (SoPC) implementation of the Whirlpool Hash Function (WHF). Realization is performed with use of embedded soft-processor NIOS II with C application for testing the WHF algorithm. Due to highly intensive computations of this cryptographic function, the hardware accelerators supporting the software solutions are introduced. This paper presents the Whirlpool Hash Function realized in several SoPC configurations, which differ in implementation complexity and performance.

The paper presents a method for bound set selection in functional decomposition targeted FPGAs with heterogeneous structure. This heuristic algorithm delivers optimal or near optimal results and is much faster than other methods.

The paper presents a logic synthesis method oriented towards FPGA architectures with specialized embedded memory blocks. Existing methods do not ensure effective utilization of possibilities provided by these specialized embedded modules. The presented method, based on balanced decomposition, leads to much more effective implementations of digital systems in modern FPGA structures.

This paper presents a Finite State Machine (FSM) implementation method based on symbolic functional decomposition. This novel approach to multilevel logic synthesis of FSMs targets Field Programmable Gate Array (FPGA) architectures. Traditional methods consist of two steps: internal state encoding and then mapping the encoded state transition table into target architecture. In the case of FPGAs, functional decomposition is recognized as the most efficient method of implementing digital circuits. However, none of the known state encoding algorithms can be considered as a good method to be used with functional decomposition. In this paper, the concept of symbolic functional decomposition is applied to obtain a multilevel structure that is suitable for implementation in FPGA architectures. The symbolic functional decomposition does not require a separate encoding step. It accepts FSM description with symbolic states and performs decomposition, producing such a state encoding that guarantees the optimal or near-optimal solution.

General functional decomposition is mainly perceived as a logic synthesis method for implementing Boolean functions into FPGA-based architectures. However it also has important applications in many other fields of modern engineering and science. In this paper, advantages of functional decomposition are demonstrated on "real life" examples. Application of decomposition-based methods in other fields of modern engineering is presented. In the case of decision tables, application of decomposition methods leads to significant benefits in the analysis process of data dependencies, especially in cases when the input decision tables are unmanageably large. Experimental results demonstrate that it can help implementing sequential machines using flip-flops or ROM memory. It also can be efficiently used as multilevel logic synthesis method for VLSI technology.

This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, performance of multipliers implemented in FPGA architectures does not allow to constructs high performance digital filters. In this paper application of distributed arithmetic is demonstrated. Since in this approach combinational LUT blocks replace general purpose multipliers, it is possible to construct digital filters of very high performance. However LUT blocks can be of considerable size thus advanced synthesis methods have to be used to map them efficiently into FPGA resources. In this paper and application of the functional decomposition based synthesis has been investigated. This method is recognised as the best synthesis method targeted FPGA architectures and allows significant improvements in digital filters implementation. The paper presents many examples confirming that decomposition allows reduction of logic cell utilisation of filter implementation based on distributed arithmetic concept with no performance degradation and even increasing it.

In recent years the functional decomposition has found an application in many fields of modern engineering and science, such as combinational and sequential logic synthesis for VLSI systems, pattern analysis, knowledge discovery, machine learning, decision systems, data bases, data mining etc. However, the lack of an effective and efficient method of the input variable partitioning limits its practical usefulness in complex systems. A classical method based on a systematic search of the whole solution space is inefficient due to its nonpolynomial time complexity. In this paper, a heuristic method for the input variable partitioning is proposed and discussed. The method is based on the application of evolutionary algorithms that allows exploring the possible solution space of a problem while keeping the high-quality solutions in this reduced space. The experimental results show that the proposed heuristic method is able to construct an optimal or near optimal solution very efficiently even for large systems. It is much faster than the systematic method while delivering results of comparable quality.

Modern FPLD devices have very complex structure. They combine PLA like structures as well as FPGA and even memory-based structures. However lack of appropriate synthesis methods do not allow fully exploiting the possibilities the modern FPLDs offer. The paper presents a general method for the synthesis targeted to implementation of sequential circuits using embedded memory blocks. The method is based on the serial decomposition concept and relies on decomposing the memory block into two blocks: a combinational address modifier and a smaller memory block. An appropriately chosen decomposition strategy may allow reducing the required memory size at the cost of additional logic cells for address modifier implementation. This makes possible implementation of FSMs that exceed available memory by using embedded memory blocks and additional programmable logic.

General functional decomposition has important applications in many fields of modern engineering and science. However, it is mainly perceived as a method of logic synthesis for implementation of Boolean functions into FPGA-based architectures. In this paper, an application of balanced functional decomposition in other fields of modern engineering is presented. The experimental results demonstrate that a method of synthesis based on functional decomposition can help in implementing sequential machines using flip-flops or ROM memory. It also can be efficiently used as a method of multilevel logic synthesis for VLSI technology.

A method for the development of a test plan for BIST-based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is based on the concept of logic cones and linear segments. Linear segments that satisfy single-generator compatibility requirement can be combinationally-exhaustively tested in parallel and are merged into a test group. The number of test groups corresponds to the number of test sessions. A tool has been developed to implement the proposed algorithm of computing logic cones and linear segments. The presented experimental results are used to develop heuristic rules that control the computing process.