This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cancelled out by decision-feedback equalizer (DFE). However, due to the existence of feedback loop in DFE, there is no trivial way to parallelize it, making it difficult to be realized in digital circuits for wireline RX based on analog-to-digital converter (ADC) with ≥ 56 Gb/s data rate. In this work, convolution theorem is applied for achieving parallel digital equalizer implementation. The digital equalizer datapath consists of discrete Fourier transform (DFT) core, inverse-DFT (IDFT) core, complex multipliers between DFT and IDFT cores, and overlap-add circuit. Design considerations for low-area VLSI implementation of such architecture is discussed.

In this letter, we show how a prefilter can be automatically adapted to open the data eye in a nonreturn to zero transmission system using only two binary samples per bit. Although the equalizer primarily aims to minimize timing jitter with a zero-forcing criterion, this equalization method also results in nearly optimum vertical eye opening, thereby causing very little overhead in complexity and power consumption. The target application is low-power high-speed serial links to transfer data between chips over a printed circuit board