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Satish M. Thatte

dblp:89/6864 · DBLP profile ↗
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6ranked-venue papers
2as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 2 first-authorApplied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Databases, data mining, and information retrieval
1 paper
Data models and query languages · 87% Database system architecture and tuning · 13%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 96% Memory systems · 4%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Data models and query languages
object-oriented database
0.011991
Object-oriented databases: design and implementation · Proc. IEEE 1991
Data models and query languages
object-oriented data model
0.011991
Object-oriented databases: design and implementation · Proc. IEEE 1991
Electronic design automation › hardware verification and test › fault modeling
functional fault model
0.021980
Test Generation for Microprocessors · IEEE Trans. Computers 1980
Efficient Algorithms for Testing Semiconductor Random-Access Memories · IEEE Trans. Computers 1978
Electronic design automation
hardware verification and test
0.021980
Test Generation for Microprocessors · IEEE Trans. Computers 1980
Efficient Algorithms for Testing Semiconductor Random-Access Memories · IEEE Trans. Computers 1978
Database system architecture and tuning
database system implementation
0.011991
Object-oriented databases: design and implementation · Proc. IEEE 1991
Electronic design automation › hardware verification and test
test generation
0.011980
Test Generation for Microprocessors · IEEE Trans. Computers 1980
Electronic design automation › hardware verification and test
memory testing
0.011978
Efficient Algorithms for Testing Semiconductor Random-Access Memories · IEEE Trans. Computers 1978
Electronic design automation › hardware verification and test › VLSI testing
microprocessor testing
0.011980
Test Generation for Microprocessors · IEEE Trans. Computers 1980

Methods — techniques the papers use, named apart from their topics

graph-theoretic modeling · 0.0fault detection algorithm · 0.0
YearPublicationVenuePosition
1991 Object-oriented databases: design and implementation
abstract
Object-oriented database systems (OODBS), which aim at meeting the data modeling, performance, cooperative design, and version management requirements of next-generation applications, such as CAD, CAM, CASE, hypermedia, and expert systems, are discussed. Key features of OODBS are presented, a taxonomy of approaches is provided, and architectural and implementation issues, design alternatives, and tradeoffs are examined. A variety of OODB systems, both research prototypes and commercial systems, are summarized. Industry efforts to accelerate a consensus that can lead to standards in the OODB are discussed.>
John Joseph, Satish M. Thatte, Craig W. Thompson, David L. Wells
Proc. IEEE2
1982 Analysis and Simulation of Parallel Signature Analyzers
Thirumalai Sridhar, D. S. Ho, Theo J. Powell, Satish M. Thatte
ITC4
1982 Concurrent Checking of Program Flow in VLSI Processors
Thirumalai Sridhar, Satish M. Thatte
ITC2
1982 An Architecture for Testable VLSI Processors
Satish M. Thatte, D. S. Ho, H.-T. Yuan, Thirumalai Sridhar, Theo J. Powell
ITC1
1980 Test Generation for Microprocessors
abstract
The goal of this paper is to develop test generation procedures for testing microprocessors in a user environment. Classical fault detection methods based on the gate and flip-flop level or on the state diagram level description of microprocessors are not suitable for test generation. The problem is further compounded by the availability of a large variety of microprocessors which differ widely in their organization, instruction repertoire, addressing modes, data storage, and manipulation facilities, etc. In this paper, a general graph-theoretic model is developed at the register transfer level. Any microprocessor can be easily modeled using information only about its instruction set and the functions performed. This information is readily available in the user's manual. A fault model is developed on a functional level quite independent of the implementation details. The effects of faults in the fault model are investigated at the level of the graph-theoretic model. Test generation procedures are proposed which take the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model. The complexity of the test sequences measured in terms of the number of instructions is given. Our effort in generating tests for a real microprocessor and evaluating their fault coverage is described.
Satish M. Thatte, Jacob A. Abraham
IEEE Trans. Computers1
1978 Efficient Algorithms for Testing Semiconductor Random-Access Memories
abstract
A fault model which views faults in semiconductor random-access memories at a functional level instead of at a basic gate level is presented. An efficient 0(n) algorithm to detect all faults in the fault model is described. The fault model is then extended to incorporate more complex faults. An 0(n · log2 n) algorithm is presented for one such extended fault model.
Ravindra Nair, Satish M. Thatte, Jacob A. Abraham
IEEE Trans. Computers2