Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Peter Salkeld Robertson

dblp:90/10971 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 1982
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Performance modeling and evaluation · 9%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
high-level synthesis
0.011982
Designing gate arrays using a silicon compiler · DAC 1982
Electronic design automation › high-level synthesis › hardware compilation
silicon compilation
0.011982
Designing gate arrays using a silicon compiler · DAC 1982
Electronic design automation
hardware verification and test
0.011982
Designing gate arrays using a silicon compiler · DAC 1982
Electronic design automation › physical design
layout automation
0.011982
Designing gate arrays using a silicon compiler · DAC 1982
Electronic design automation
physical design
0.011982
Designing gate arrays using a silicon compiler · DAC 1982
Performance modeling and evaluation
simulation
0.011982
Designing gate arrays using a silicon compiler · DAC 1982
YearPublicationVenuePosition
1982 Designing gate arrays using a silicon compiler
abstract
This paper describes a programming environment in which gate array designs can be developed. It allows the engineer to design for performance, wirability and testability by manipulating a textual description of a design. The principle features of this are a high-level language for design description, completely automatic layout, and an integrated simulator. The total package can be referred to as a silicon compiler in the gate array design style.
John P. Gray, Irene Buchanan, Peter Salkeld Robertson
DAC3