Third-party intellectual property cores are essential building blocks of modern digital hardware. However, they usually come from vendors of different trust levels and may contain undocumented design functionality. Distinguishing such stealthy malicious design modifications remains a significant research challenge. State-of-the-art hardware Trojan detection methods usually require expert knowledge, sophisticated tools or large volumes of training samples. In this work, we make a step towards design for assurance by developing a Trojan detection method targeting look-up-table (LUT) netlists, which exploits the rich explicit structural and behavior characteristics embedded in the initialization vectors of LUTs to pinpoint Trojans. The proposed method automatically extracts a small set of high-quality Trojan related properties and detects Trojans through formal verification of the extracted properties, eliminating the limitation of manual property specification while covering a much wider range of Trojan designs. We further present a defense solution to mitigate the identified Trojans through lightweight design reconfiguration to neutralize the Trojan payload. The proposed method can be seamlessly integrated into the standard EDA flow to enable security to be evaluated along with functional correctness and performance budgets. Experimental results have demonstrated that our method can detect and mitigateTrust-Hub,ATTRITIONas well as satisfiability don't care Trojans.

Black-box neural networks are inherently inscrutable, and their widespread use has triggered significant societal issues in crucial areas such as healthcare, finance and safety. In these high-stakes decision-making domains, the deployment of machine learning algorithms requires not only prediction accuracy but also their interpretability and robustness against data distribution shifts, such as outliers, label noise, and category imbalance. In this work, we propose a novel Meta-weighted Sparse Neural Additive Model (MSpNAM), which offers robustness through an efficient bilevel weighting policy and inherits strong explainability and representation capabilities from the additive modeling strategy. Furthermore, empirical results across multiple synthetic and real datasets, under various distribution shifts, demonstrate that MSpNAM can scale effectively and achieve superior performance in terms of robustness, interpretability, and anti-forgetting compared to some of the latest baselines.

Trojans represent a severe threat to hardware security and trust. This work investigates the Trojan detection problem from a unique viewpoint and proposes a novel hardware Trojan localization method targeting FPGA netlists. The proposed method automatically extracts the rich structural and behavioral features at look-up-table (LUT) level to train an explainable graph neural network (GNN) model for classifying design nodes in FPGA netlists and identifying the Trojan-infected ones. Experimental results using 183 hardware Trojan benchmarks show that our method successfully pinpoints Trojan-infected nodes with true positive rate, accuracy and area under the ROC curve (AUC) of 95.14%, 95.71% and 95.46% respectively. To the best of our knowledge, this is the first LUT level Trojan localization solution using explainable GNNs.

As the core engine of modern communication systems, digital circuits are encountering significant security risks of cyber-attacks. Hardware information flow tracking (IFT) is a powerful tool for integrated circuit design security verification and vulnerability detection. While there are a large body of hardware IFT methods at different levels of abstraction, look-up-table (LUT) level IFT is still an open research challenge due to the huge number of possible LUT configurations that all correspond to varying IFT behaviors. In this work, we make the first move towards LUT level IFT for field programmable gate array (FPGA) design security verification. Specifically, we design an algorithm that enables automatic creation of the precise IFT model for an arbitrary LUT and the generation of fine-grained IFT logic for FPGA netlists. Through using the generated IFT logic as the security model, we can formally prove security properties and hunt for security vulnerabilities. Experimental results have demonstrated that our method can detect the timing channels and hardware Trojans residing in the synthesized FPGA netlists of Trust-Hub benchmarks. Our work complements the spectrum of hardware security verification solutions at both the FPGA netlist and bitstream ends, which fills in the gap of post-synthesis FPGA design security verification tools.

Hardware Trojans are malicious design modifications, which pose severe threats to hardware security and trust. Since integrated circuit (IC) designs are difficult to modify after chip fabrication, it is of great importance to detect Trojans in the early design stage. In this work, we propose a novel hardware Trojan detection method at register transfer level (RTL) through semantic feature extraction and natural language processing (NLP). We convert the hardware design to control and data flow graph (CDFG) and develop a depth-first search and sliding window based algorithm for extracting and segmenting paths. This process preserves the structural and semantic features of RTL code. We then employ the NLP technique to perform Trojan detection at the granularity of RTL code statement. Specifically, we train the FastText model, which is proficient in word representation and text classification, to precisely pinpoint the Trojan-infected statements. We further integrate the word bigram features during the training process to improve the Trojan detection performance. Experimental evaluations using Trust-Hub benchmarks show that the proposed method can successfully pinpoint hardware Trojans with true positive rate (TPR), true negative rate (TNR), accuracy and F1-score of 97.77%, 99.95%, 98.86% and 97.46% respectively on average.

Software attacks that exploit the hardware security vulnerabilities of processors have become new breakthrough points for hackers, which pose severe threats to hardware security and trust. This paper proposes a novel system security verification method based on instruction set architecture (ISA) level information flow tracking (IFT), which is capable of modeling and checking security properties in both software and hardware designs. We use RISC-V system as a demonstration, which is a lately developed open-source ISA widely used in Internet of Things and is facing severe security threats due to the universal interconnection of devices. By developing RISC-V software and hardware IFT models, security properties including confidentiality and integrity can be verified and vulnerabilities can be detected. Experimental results show that the proposed verification method can detect software security threats and hardware security vulnerabilities in the RISC-V processor design.

Trojan horses represent a major threat to hardware security and trust. In this work, we propose a novel hardware Trojan detection method based on explainable graph neural networks (GNNs) targeting FPGA netlists. We leverage the rich explicit structural features and behavioral characteristics at LUT, which offers an ideal abstraction level and granularity for Trojan detection. A GNN model with optimized class-balanced focal loss is trained for automated Trojan feature extraction and classification. Based on the Granger causality theory, we develop an interpretable approach to explain the decision mechanism of our GNN model. Experimental evaluations using 927 Trust-Hub hardware Trojan benchmarks and 262 Trojan free open source IP cores show that the proposed method provides promising detection results with accuracy, precision and F1-measure of 98.78%, 99.69% and 99.23% for Xilinx FPGA netlists while 97.93%, 97.87% and 98.51% for Intel FPGA netlists respectively. The experiment results have demonstrated that the proposed explainable approach can successfully identify the essential components that contribute to accurate Trojan classification and provide interpretable explanation for the GNN model.

Recently, adversarial metric learning has been proposed to enhance the robustness of the learned distance metric against adversarial perturbations. Despite rapid progress in validating its effectiveness empirically, theoretical guarantees on adversarial robustness and generalization are far less understood. To fill this gap, this paper focuses on unveiling the generalization properties of adversarial metric learning by developing the uniform convergence analysis techniques. Based on the capacity estimation of covering numbers, we establish the first high-probability generalization bounds with order O(n^{-1/2}) for adversarial metric learning with pairwise perturbations and general losses, where n is the number of training samples. Moreover, we obtain the refined generalization bounds with order O(n^{-1}) for the smooth loss by using local Rademacher complexity, which is faster than the previous result of adversarial pairwise learning, e.g., adversarial bipartite ranking. Experimental evaluation on real-world datasets validates our theoretical findings.

Neural networks have been successfully applied in numerous domains with the help of high-quality training samples. However, datasets containing noises and outliers (i.e., corrupted samples) are ubiquitous in the real world. When using these datasets as training samples, most neural networks exhibit poor predictive performance. In this paper, motivated by the modal regression, we propose a Modal Neural Network, which is robust to corrupted samples. Specifically, the modal neural network can reveal the most likely trends of training samples without overfitting the corrupted samples. On the theoretical side, we establish the generalization error bounds of the proposed method with Rademacher complexity. On the experimental side, the numerical results demonstrate our method yields substantial effectiveness and robustness to different levels of corruption on both synthetic and real-world benchmark datasets. Furthermore, our method, as a plug-and-play algorithm, can be readily applied to most neural network architectures and optimizers.

State-of-the-art EDA tools largely employ functional circuit models that are inadequate for verifying and emulating design properties related to fault effect and tolerance. In this paper, we derive fully synthesizable fault effect propagation models for formally reasoning about fault-related design behaviors under different types of faults. We associate each signal bit with a binary fault label to reflect its fault attribute. We further derive fine-granularity precise propagation policies and specify these policies as formal models for fault effect analysis using functional EDA tools. Experimental results using IWLS benchmarks have demonstrated that our formal models can be used to measure fault propagation effects and accelerate fault verification through hardware emulation. Our work makes a step towards property driven EDA flows that allow fault tolerance and dependability to be verified alongside functional correctness.

Taint-propagation and X-propagation analyses are important tools for enforcing circuit design properties such as security and reliability. Fundamental to these tools are effective models for accurately measuring the propagation of information and calculating metadata. In this work, we formalize a unified model for reasoning about taint- and X-propagation behaviors and verifying design properties related to these behaviors. Our model are developed from the perspective of information flow and can be described using standard hardware description language (HDL), which allows formal verification of both taint-propagation (i.e., security) and X-propagation (i.e., reliability) related properties using standard electronic design automation (EDA) verification tools. Experimental results show that our formal model can be used to prove both security and reliability properties in order to uncover unintended design flaw, timing channel and intentional malicious undocumented functionality in circuit designs.

Consortium blockchain has been widely used in different scenarios, where blockchain members demand that their uploaded data could be audited under their identities without exposing the data themselves. However, so far, no solution of privacy-preserving data auditing has been proposed. To address the problem, we propose zkrpChain, which focuses on protection of the integrity and privacy of the data uploaded by blockchain members while leaving their identities public. In zkrpChain, which is based on Hyperledger Fabric and Bulletproofs, both standard-range and arbitrary-range zero-knowledge range proofs generation and verification are supported. To improve the efficiency, the aggregation of multiple proofs and batch verification are also developed. For further development, we provide the client codes, chaincodes and related APIs. Finally, we conduct experiments to evaluate the performance of zkrpChaln, and the results show that the consumed time (in an 8-thread scheme) of chaincodes and needed on-chain space of zkrpChain are very close to Bulletproofs, which is evaluated in a single-machine environment.

The testing, verification and evaluation of wireless systems is an important but challenging endeavor. The most realistic method to test a wireless system is a field deployment. Unfortunately, this is not only expensive but also time consuming. In this paper, we present the design and implementation of a digital wireless channel emulator, which connects directly to a number of radios, and mimics the wireless channels between them, across a range of scenarios, in real-time. We use high-level synthesis tools to design the emulator while performing design space exploration. We describe the optimizations and tradeoffs that were necessary to reach the target throughput and area requirements.