Progress in VLSI technology is driven by increasing circuit density through process scaling, but with shrinking geometry comes an increasing threat to reliability. FPGAs are uniquely placed to tackle degradation and faults due to their regular structure and ability to reconfigure, giving them the potential to implement system-level reliability enhancements. To assess the scale of the challenge, a method for measuring and monitoring degradation in an FPGA was developed and used to conduct an accelerated life test on a modern device. This revealed a clear, gradual degradation in timing performance that matches the expected effects of Negative-Bias Temperature Instability and Hot Carrier Injection, two of the most important VLSI degradation mechanisms. Further insight into ageing phenomena was gained using modelling -- showing how degradation in a typical LUT would be affected by different usage conditions, and predicting in detail the effects on circuit behaviour.

Two complementary techniques for reducing the effect of within-die variability on the critical path delay in FPGA circuits are reported. The first technique selects the best LUT mapping from a set of alternative mappings of a logic function for each LUT cluster in the FPGA. The second selects the best assignment of LUTs to physical locations within a cluster. The techniques can be used together, and are shown in Monte Carlo experiments to reduce both the mean and standard deviation of critical path delay.

This paper presents two new design methodologies for throughput-centric wave-pipelined interconnects: cascaded buffers insertion and transistor sizing. Experimental results show that up to 185% throughput improvement can be achieved by applying the new proposed approaches compared with conventional interconnect optimization techniques, such as buffer insertion. Moreover, with the combination of cascaded buffers insertion and adequate techniques in supply voltage scaling, up to 60% dynamic power reduction can be gained compared to the conventional design.

This article proposes a Built-In Self-Test (BIST) method to accurately measure the combinatorial circuit delays on an FPGA. The flexibility of the on-chip clock generation capability found in modern FPGAs is employed to step through a range of frequencies until timing failure in the combinatorial circuit is detected. In this way, the delay of any combinatorial circuit can be determined with a timing resolution of the order of picoseconds. Parallel and optimized implementations of the method for self-characterization of the delay of all the LUTs on an FPGA are also proposed. The method was applied to Altera Cyclone II and III FPGAs . A complete self-characterization of LUTs on a Cyclone II was achieved in 2.5 seconds, utilizing only 13kbit of block RAM to store the results. More extensive tests were carried out on the Cyclone III and the delays of adder circuits and embedded multiplier blocks were successfully measured. This self-measurement method paves the way for matching timing requirements in designs to FPGAs as a means of combating the problem of process variations.

Global interconnection is fundamental to high bandwidth links for inter-module communication in FPGAs. The long range global interconnections at high clock frequencies are becoming more problematic. This is due to the large circuit delay and leakage power caused by interconnect switches along the line. The delay is worsen by the global interconnect deterioration in technology scaling. In this paper, we address this problem by presenting an interconnect wave-pipelining strategy by using the existing programmable interconnects fabrics to provide high-throughput global communication in FPGA. A novel global interconnection circuit model is presented and, from the model, interconnection throughput can be derived. The model has been verified using SPICE simulation and delay results from the Xilinx FPGA Editor. We demonstrate the feasibility of our proposal by implementing a wave-pipelined interconnect circuit in a Xilinx Virtex-5 FPGA device. The circuit is able to achieve a throughput that is 3 times faster than a conventional synchronous approach. We conclude this paper by having a discussion about two strategies to further enhance the wave-pipelining throughput

As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. To avoid significant performance loss through pessimistic over-design new design strategies are required that are cognizant of within-die performance variability. This paper examines the effect of variability on the clock resources in FPGA devices. Techniques and circuits for measuring clock skew variations are presented, with initial results indicating that skew variability is at least as significant as signal path variability in modern FPGAs. A model of variation in FPGA clock networks is proposed, and used to suggest strategies for reducing the impact of variations on the performance of implemented designs

Reliability and process variability are serious issues for FPGAs in the future. Fortunately FPGAs have the ability to reconfigure in the field and at runtime, thus providing opportunities to overcome some of these issues. This paper provides the first comprehensive survey of fault detection methods and fault tolerance schemes specifically for FPGAs, with the goal of laying a strong foundation for future research in this field. All methods and schemes are qualitatively compared and some particularly promising approaches highlighted.

The goal of this PhD project is to devise a way to combat the effect of process variation on propagation delays in modern FPGAs. Through our research, we have devised a novel measurement method that is capable of measuring the delays of components on FPGAs with picosecond timing resolution and fine spatial granularity. The method avoids the use of external test equipment and able to measure stochastic delay variability, which is becoming increasingly significant. The aim is to exhaustively test FPGA components based on this method and use the results to optimise the placement and routing of circuits in FPGAs to maximise performance under the negative influence of process variation.

On-FPGA communication is becoming more problematic as the long interconnection performance is deteriorating in technology scaling. In this paper, we address this issue by presenting a new wave-pipelined signaling scheme to achieve high-throughput communication in FPGA. The throughput and power consumption of a wave-pipelined link have been derived analytically and compared to the conventional synchronous link. Two circuit designs are proposed to realize wave-pipelined link using FPGA fabrics. The proposed approaches are also compared with conventional synchronous and asynchronous pipelining techniques. It is shown that, the wave-pipelined approach can achieve up to 5.66 times improvement in throughput versus the synchronous link and 13% improvement in power consumption and 35% improvement in delay versus the synchronous register-pipelining. Also, trade-offs between power, speed and area between the proposed and conventional designs are studied.

As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. To avoid significant performance loss through pessimistic over-design new design strategies are required that are cognisant of within-die performance variability. This paper examines the effect of process variability on the clock resources in FPGA devices. A model of variation in clock skew in FPGA clock networks is presented. Techniques for reducing the impact of variations on the performance of implemented designs are proposed and analysed, demonstrating that skew variation can be reduced by 70% or more through a combination of phase adjustment and clock rerouting. Measurements on a Virtex-5 FPGA validate the feasibility and benefits of the proposed compensation strategies.

This paper proposes a novel test method for measuring the worst case path delay of any circuit on an FPGA, combinatorial or sequential, where little prior knowledge of the circuitpsilas internal structure is required. The method is based on detecting changes in the transition probability profile on the circuitpsilas output nodes while a range of test clock frequencies is stepped through. The method is applied to three classes of circuits, all implemented on an Altera Cyclone III FPGA: an adder carry chain, an embedded multiplier and a linear-feedback shift-register. The measured delays are compared to that found by a previously published, but much more time consuming, method and their results match to within 12%.

Variations in the semiconductor fabrication process results in differences in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. Field-Programmable Gate Arrays may be able to compensate for within-die delay variability, by judicious use of reconfigurability. This article presents two strategies for compensating within-die stochastic delay variability by using reconfiguration: reconfiguring the entire FPGA, and relocating subcircuits within an FPGA. Analytical models for the theoretical bounds on the achievable gains are derived for both strategies and compared to models for worst-case design as well as statistical static timing analysis (SSTA). All models are validated by comparison to circuit-level Monte Carlo simulations. It is demonstrated that significant improvements in circuit yield and timing are possible using SSTA alone, and these improvements can be enhanced by employing reconfiguration-based techniques.

Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re-configurability of Field-Programmable Gate Arrays presents the opportunity to compensate for within-die delay variability. This paper presents three reconfiguration-based strategies for compensating within-die stochastic delay variability in FPGAs: reconfiguring the entire FPGA, relocating subcircuits within an FPGA, and reconfiguring signal paths within a design. The yield of each strategy is analysed and compared with worst-case design and statistical static timing analysis (SSTA). It is demonstrated that significant im-provements in circuit yield and timing are possible using SSTA alone, and these improvements can be enhanced by employing reconfiguration-based techniques.

This paper proposes a built-in self-test (BIST) method to measure accurately the combinatorial circuit delays on an FPGA. The flexibility of the on-chip clock generation capability found in modern FPGAs is employed to step through a range of frequencies until timing failure in the combinatorial circuit is detected. In this way, the delay of any combinatorial circuit can be determined with a timing resolution of 1 ps or lower. A parallel implementation of the method for self-characterization of the delay of all the LUTs on an FPGA is also proposed. The method was applied to an Altera Cyclone-II FPGA (EP2C35). A complete self-characterization was achieved in 3 seconds, utilizing only 13 kbit of block RAM to store the results. This self-characterization method paves the way for matching timing requirements in designs to FPGAs as a means of combating the problem of process variations.

Dynamic routing can substantially enhance the quality of service for multiprocessor communication, and can provide intelligent adaptation of faulty links during run time. Implementing dynamic routing on a network-on-chip (NoC) platform requires a design that provides highly efficient optimal path computation coupled with reduced area and power consumption. In this paper, we present a hybrid analog-digital routing network design that enables efficient dynamic routing on an NoC architecture. The digital part provides accurate real-time traffic estimation using a temporal cost evaluation and adaptation scheme. The analog network, which is distributed within the digital communication network, provides an efficient implementation for the optimal routing algorithm with extremely low power consumption. Our results demonstrate the effectiveness of the hybrid analog-digital design, with a significant improvement in latency over the static routing for random hot spot traffics

Embedded systems in field-programmable gate arrays (FPGAs) can be customized and adaptive if assembled from modular components at run time. This paper examines realizing run-time system assembly by extension of platform-based design. Two major challenges are addressed in this paper. First, the design of a reconfigurable platform architecture suitable for run-time system assembly is described. Different systems are constructed by integrating the platform architecture with different modular components, which employ the communication infrastructure supplied by the platform in order to interact. Second, where on-chip communications channels use shared media, we propose techniques for modeling the intermodule communication behavior based on statistical time-division multiplexing. The proposed techniques enable system designers to guarantee that logical communication requirements between the adjunct modules can be satisfied by the infrastructure. An in-depth analysis is presented and then verified with cycle-accurate simulations for an example reconfigurable platform for real-time video applications.

The recent development of Platform-FPGA or Field-Programmable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potential for immense computing power as well as opportunities for rapid system prototyping. These platforms require high-performance on-chip communication architectures for efficient and reliable inter-processor communication. However, as the number of embedded processors increases, communication bandwidth between embedded components becomes a limiting factor to overall system performance. In this paper, we survey the state-of-the-art on-FPGA communication architectures and methodologies. Salient factors, which include quantitative performance metrics and qualitative factors, relevant to design are identified and used to analyze and classify the on-FPGA communication architectures. This survey aims to facilitate innovation in and development of future on-FPGA communication architectures.

Semiconductor scaling causes increasing and unavoidable within-die parametric variability. This paper describes accurate measurement techniques for characterising both systematic and stochastic delay variability in FPGAs. Results and analysis are presented from measurements made on a sample of 90nm devices, showing that delay per logic element varies stochastically by plusmn3.54% on average over the set. The delay also varies by up to 3.66% across a single die from correlated sources of variability. The results are extrapolated to determine the impact at future technology nodes. The predicted significant performance degradation that variability will cause demonstrates the importance of new circuit or system design techniques to cope with variations in future FPGAs

Modular systems implemented on Field-Programmable Gate Arrays can benefit from being able to load and unload modules at run-time, a concept that is of much interest in the research community. While dynamic partial reconfiguration is possible in Virtex series and Spartan series FPGAs, the configuration architecture of these devices is not amenable to modular reconfiguration, a limitation which has relegated research to theoretical or compromised resource allocation models. In this paper two methods for implementing modular dynamic reconfiguration in Virtex FPGAs are compared and contrasted. The first method offers simplicity and fast reconfiguration times, but limits the geometry and connectivity of the system. The second method, recently developed by the authors, enables modules to be allocated arbitrary areas of the FPGA, bridging the gap between theory and reality and unlocking the latent potential of partial reconfiguration. The later method has been demonstrated in three applications.

The ever increasing quantities of logic resources combined with heterogeneous integrated performance enhancing primitives in high-end FPGAs creates a design complexity challenge that requires new methodologies to address. We present a structured system based design methodology which aims to increase productivity and exploit reconfigurability in large scale FPGAs. The methodology is exemplified by sonic-on-a-chip, a video image processing system.