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Lovleen Bhatia

dblp:90/1616 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 94% Embedded and real-time systems · 6%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
formal verification
0.122007
Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation · DAC 2007
Directed-simulation assisted formal verification of serial protocol and bridge · DAC 2006
Electronic design automation › hardware verification and test
hardware verification
0.112007
Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation · DAC 2007
Electronic design automation › hardware verification and test › formal verification
sequential equivalence checking
0.112007
Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation · DAC 2007
Electronic design automation
hardware verification and test
0.112006
Directed-simulation assisted formal verification of serial protocol and bridge · DAC 2006

Methods — techniques the papers use, named apart from their topics

semi-formal techniques · 0.1abstract interpretation · 0.1simulation · 0.1black-box verification · 0.1
YearPublicationVenuePosition
2007 Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation
abstract
For multimedia SOCs supporting real time, high throughput and data intensive applications, performance validation of memory subsystems is needed to uncover the bottlenecks in the RTL implementation. Traditional validation techniques are either too slow, non-exhaustive (like performance simulations or running pseudo applications on FPGA platforms), or are not accurate enough to guarantee conformance (like abstract interpretation and analysis). In this paper we present an approach for performance validation which uses (a) semi-formal techniques rather than pure simulation for providing a wider coverage, (b) actual RTL implementations wherever available for more accurate analysis, and (c) sequential equivalence checking for validating the abstract models for IP's whose RTL is either not present or from which datapath has been abstracted out. We illustrate this approach using two case studies from video signal processing platforms. In the first study, performance Issues found in silicon were detected using the proposed approach, and in the second study a number of performance bottlenecks were detected much before the RTL was frozen.
Lovleen Bhatia, Jayesh Gaur, Praveen Tiwari, Raj S. Mitra, Sunil H. Matange
DAC1
2006 Directed-simulation assisted formal verification of serial protocol and bridge
abstract
Robust verification of protocol conversion and arbitration schemes of SoC bridges forms a significant component of the overall SoC verification. Formal verification provides a way to achieve this, but a naive approach often leads to explosion of the state space, and is impractical for most of today's protocols and bridges. This problem is further complicated in the presence of serial protocols, where control and data are mixed together and transactions continue for very great depths. White-box verification is not a feasible solution, since these bridges are often imported or generated from other sources, and internal information is not readily available. In this paper, we propose a black-box and hybrid approach to this problem, by judiciously mixing simulation and formal verification. We illustrate our approach by applying it to two dual stage bridges that perform serial to parallel protocol conversion and vice versa.
Saurav Gorai, Saptarshi Biswas, Lovleen Bhatia, Praveen Tiwari, Raj S. Mitra
DAC3