Inter-modulo arithmetic operations, such as reverse conversion and scaling, are important but difficult operations in the RNS domain. This paper proposes efficient arithmetic units to perform this hard class of RNS operations for a new family of augmented three-moduli sets {2n+k,2n−1,2n+1−1}(0≤k≤n)⁠. Experimental results for 65 nm CMOS technology show that the proposed reverse converter reduces the delay by about (17.6−33.4)% in comparison with the state of the art. Moreover, this work presents the first architecture of a scaler dedicated for this augmented three-moduli sets.

The scaling problem in Residue Number System was addressed in many publications. A significant focus was given to scale the three moduli set$(2^{n}-1, 2^{n}, 2^{n}+1)$by$2^n$, where$n$is a positive integer. This paper presents a scaling structure design for the moduli sets$(2^{n}-1, 2^{n+p}, 2^{n}+1)$scaled by$2^n$, where$0\leq p \leq n$. The new design has the delay of a full-adder and a modular adder. The proposed structure is smaller, faster and more power-efficient than the most recent published work for the same moduli set and the same scaling factor. VLSI synthesis results showed an average area reduction of$(9.8-27.9)$percent, an average time reduction of$(13.9-20.8)$percent and an average power reduction of$(15.9-22.3)$percent. The paper also presents a time-efficient scaling structure for the extended three moduli set$(2^{n}-1, 2^{n+p}, 2^{n}+1)$scaled by$2^{n+p}$, where$1\leq p \leq n$. The delay of this structure is one half-adder more than the delay of the aforementioned structure.

This brief presents a residue-to-binary converter for the moduli set {2n- 1, 2n+ 1, 22n+ 1, 22n+p}, where n is a positive integer and 0 ≤ p ≤ n - 2. The converter consists of three simplified 4n-bit carry-save adders (CSAs) along with a modulo (24n-1) adder. The main contribution of this brief is reducing the requirements of the proposed CSA network, which has impacted the area, delay, power and energy. Compared with four-moduli and five-moduli sets that have the dynamic range 2v(24n-1), where v = n or 2n, the proposed converter resulted in the average area, delay, power, and energy reductions of 22.7%, 9.2%, 17.8%, and 24.5%, respectively. Moreover, the throughput rate per unit area has been improved by an average of 48.7%.

This paper presents a structure for a sign detector that is suitable for a group of three-moduli sets. This group is defined by (2n+p, 2n- 1, 2n+ 1), where n and pare any positive integers such that 0 ≤ p <; n. The dynamic range of this group consists of (3n + p) bits and the proposed structure can be easily changed to accommodate different values of p. When compared with other previously presented structures, the sign detector proposed in this paper proved to be more efficient in terms of area, delay and power.

This paper introduces two arithmetic decoders that decode the residue number system into its binary equivalent. The first one deals with the moduli set: (2/sup n/,2/sup n/-1,2/sup n/+1,2/sup n/-2/sup (n+1/2)/+1,2/sup n/+2/sup (n+1/2)/+1), while the other deals with the moduli set: (2/sup n+1/,2/sup n/-1,2/sup n/+1,2/sup n/-2/sup (n+1/2)/+1,2/sup n/+2/sup (n+1/2)/+1), where n is odd. Compact forms for the multiplicative inverse of each modulus is introduced, which facilitates the implementation of these arithmetic decoders. The proposed hardware realizations for these decoders are based on using six carry save adders and one carry propagate adder. The hardware and time requirements of these decoders are much better than other similar decoders found in literature. A sub-micron silicon implementation for the decoder has been performed and reported.

The family of moduli that has the form (2n − (2p ± 1)) is considered in this paper. A suggestion for a fast residue multiplier for this family of moduli is introduced. The multiplication algorithm proposed in this paper generates (2n + p − 2) partial products; however, it compresses the magnitude of each partial product to be less than 2n. Although it requires an additional integrated circuit area compared with the most recent published study, the new proposed modular multiplier has a logarithmic delay, which makes it faster than any other modular multiplier. Moreover, it is even faster than binary-based iterative array multipliers with a final CLA addition. The proposed modular multiplier is very suitable for medium and large dynamic ranges.

A modular adder is a very instrumental arithmetic component in implementing online residue-based computations for many digital signal processing applications. It is also a basic component in realizing modular multipliers and residue to binary converters. Thus, the design of a high-speed and reduced-area modular adder is an important issue. In this paper, we introduce a new modular adder design. It is based on utilizing concepts developed to realize binary-based adders. VLSI layout implementations and comparative analysis showed that the hardware requirements and the time delay of the new proposed structure are significantly, less than other reported ones. A new modulo (2/sup n/+1) adder is also presented. Compared with other similar ones, this specific modular adder requires less area and time delay.

Modular multiplication is a very important arithmetic operation in residue-based real-time computing systems. In realizing these multipliers, ROM-based structures are more efficient for small moduli. Due to the exponential growth of ROM sizes, implementations with arithmetic components are more suitable for medium and large moduli. This paper presents a new modular multiplier that can deal efficiently with medium and large size moduli. The design of this modular multiplier that multiplies two n bit residue digits consists, basically, of a (n/spl times/n) binary multiplier, a ((n-1-k)/spl times/k) binary multiplier (k

In this paper we introduce a new algorithm for division in residue number system, which can be applied to any moduli set. Simulation results indicated that the algorithm is faster than the most competitive published work. To further improve this speed, we customize this algorithm to serve two specific moduli sets: (2k, 2k−1, 2k−1−1) and (2k+1, 2k, 2k−1). The customization results in eliminating memory devices (ROMs), thus increasing the speed of operation. A semi-custom VLSI design for this algorithm for the moduli (2k+1, 2k, 2k−1) has been implemented, fabricated and tested.

In 1995 the authors introduced the main outlines of a new algorithm for division in residue number system, which can be applied to any moduli set. Simulation results proved that the algorithm was many times faster than most competitive published work. Determining the position of the most significant nonzero bit of any residue number in that algorithm is the major speed limiting factor. They customize the same algorithm to serve two specific moduli sets: (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) and (2/sup k/+1, 2/sup k/, 2/sup k/-1), and thus, eliminate that speed limiting factor. Based on this work, hardware needed to determine most significant bit position has been reduced to a single adder. Therefore, computation time and hardware requirements are substantially improved. This would enable RNS to be a stronger force in building general purpose computers.

A new algorithm for one of the longstanding problems in residue number system, namely division, is presented. The algorithm is very simple. It approaches the paper-and-pencil division procedure where the quotient is selected to guarantee a non-negative remainder. This algorithm does not require sign and overflow detection, scaling, or redundant moduli. Based on computer simulation results, the algorithm is four times faster than the most recent and competitive published work by Lu and Chiang (see IEEE Trans. Compu., vol. C-41, no. 8, p. 1026-32, 1992).