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Nico Bannow

dblp:90/2630 · DBLP profile ↗
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8ranked-venue papers
2as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 6 · 2 first-authorSystems, architecture and hardware · 4 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 67% Embedded and real-time systems · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Embedded and real-time systems
automotive electronics
0.212014
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges · DAC 2014
Electronic design automation
hardware verification and test
0.212014
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges · DAC 2014
Electronic design automation › system-level design
virtual prototyping
0.212014
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges · DAC 2014

Methods — techniques the papers use, named apart from their topics

virtual prototyping · 0.2
YearPublicationVenuePosition
2019 Flexible Data Flow Architecture for Embedded Hardware Accelerators
Jens Froemmer, Nico Bannow, Axel Aue, Christoph Grimm 0001, Klaus Schneider 0001
ICA3PP (1)2
2014 Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges
abstract
Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults.
Jan-Hendrik Oetjens, Nico Bannow, Markus Becker 0001, Oliver Bringmann 0001, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Grüttner, Thomas Kruse, Christoph Kuznik, Hoang Minh Le 0001, Andreas Mauderer, Wolfgang Müller 0003, Daniel Mueller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter 0003, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
DAC2
2013 Advanced features for industry-level logging and tracing of C-based designs
Wei Hong 0005, Jyoti Joshi, Alexander Viehl, Nico Bannow, Angela Kramer, Hendrik Post, Oliver Bringmann 0001, Wolfgang Rosenstiel
FDL4
2010 Mixed Signal Simulation with SystemC and Saber
Tobias Kirchner, Nico Bannow, Christian Kerstan, Christoph Grimm 0001
FDL2
2009 Analogue mixed signal simulation using spice and SystemC
abstract
SystemC is a discrete event simulator that enables the programmer to model complex designs with varying levels of abstraction. In order to improve precision, it can be coupled to more specialized simulators. This article introduces the concept of loose simulator coupling between an analogue simulator and SystemC. It explains the properties and advantages which include a higher simulation performance as well as a higher degree of flexibility. A design example in which SystemC will be connected to SwitcherCad will demonstrate the benefits of loose coupling.
Tobias Kirchner, Nico Bannow, Christoph Grimm 0001
DATE2
2008 Enabling Automated Code Transformation and Variable Tracing
abstract
To solve the challenge of hardware/software partitioning and the reuse of legacy system models (Bannow et al., 2004) introduced a module adapter (MA) based approach which is considered in section 2. The described transformation/mapping of functional code into a SystemC model still needs heavy code modifications. Besides the parser that has to be nearly as powerful as a C++ compiler the readability suffers from the necessary changes. This paper introduces an approach which reduces the code modifications to a minimum. The primary objective is to provide a solution to enable an automated application. In this novel approach, code readability and transformation effort are improved significantly by using the powerful operator overloading mechanism of C++. The presented implementation can be used to either realize transparent communication over module barriers, trace simulation data or only for debugging purposes. Some examples demonstrate the applicability and give some incitements for expedient use cases. The presented C++ code can be easily extended by inheritance for custom needs.
Christian Kerstan, Nico Bannow, Wolfgang Rosenstiel
FDL2
2004 Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications
abstract
In this paper we present results in using the new object-oriented design approach OSSS (ODETTE system synthesis subset). The methodology and tools of the ODETTE (object-oriented co-design and functional test techniques) project have been developed within the context of the IST programme of the European Commission. Main focus of OSSS lies in the field of hardware design and in synthesis capability. The strategy is based on an extension of the synthesizable subset of standard systemC. The approach supports real object-oriented and synthesizable design features like classes, inheritance, templates, polymorphism and global object access. Therefore OSSS promises high efficiency in sense of capability to handle complex designs, faster development time, improved code quality and faster time to market. In contrast, standard systemC is also based on C++ constructs, but no object-oriented constructs are available yet for a synthesizable system description. We have evaluated OSSS on an automotive design example. It was chosen for the implementation of a component that is part of all video projects: A camera's exposure control unit (ExpoCU). The first main goal that was achieved is a synthesizable design by the automatic generation of an FPGA netlist from an OSSS description. Furthermore we have also proved the methodology to fulfill industrial requirements such as usability for complex system development, integration of existing IP, improved code quality and decreased development effort. Comparison will be done against existing VHDL based design flow. We especially focus on the implementation and testability by comparing the new object-oriented synthesis approach with a standard VHDL flow by laying emphasis on synthesizability. OSSS and equivalent kinds of methodology show a large potential to handle new generations of complex HW-SW systems. Moreover the gap between increasing design complexity and available methodologies already now gets bigger and bigger and thus needs to be closed by new solutions such as OSSS.
Nico Bannow, Karsten Haug
DATE1
2004 Performance Analysis and Automated C++ Modularization Using Module-Adapters for SystemC
Nico Bannow, Karsten Haug, Wolfgang Rosenstiel
FDL1