This paper presents a novel low-transition linear feedback shift register (LFSR) that is based on some new observations about the output sequence of a conventional LFSR. The proposed design, called bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 times 1 multiplexer. When used to generate test patterns for scan-based built-in self-tests, it reduces the number of transitions that occur at the scan-chain input during scan shift operation by 50% when compared to those patterns produced by a conventional LFSR. Hence, it reduces the overall switching activity in the circuit under test during test applications. The BS-LFSR is combined with a scan-chain-ordering algorithm that orders the cells in a way that reduces the average and peak power (scan and capture) in the test cycle or while scanning out a response to a signature analyzer. These techniques have a substantial effect on average- and peak-power reductions with negligible effect on fault coverage or test application time. Experimental results on ISCAS'89 benchmark circuits show up to 65% and 55% reductions in average and peak power, respectively.

An element-by-element preconditioned conjugate gradient (PCG) iterative solver for the solution of 3D finite element analysis has been implemented into a FPGA-based 32-bit floating-point reconfigurable computer. The algorithm formulation has been chosen in order to optimize the match with the capabilities of the FPGA platform. It is capable of giving a speed-up of about 40 times compared to an optimized 64-bit software version running on a fast PC.

Speech recognition is a computationally demanding task, particularly the stage which uses Viterbi decoding for converting pre-processed speech data into words or sub-word units. We present an FPGA implementations of the decoder based on continuous hidden Markov models (HMMs) representing monophones, and demonstrate that it can process speech 75 times real time, using 45% of the slices of a Xilinx Virtex XCV1000.

The Discrete Element Method (DEM) is a numerical model to describe the mechanical behaviour of discontinuous bodies. It has been traditionally used to simulate particle flows (e.g. sand, sugar), but is becoming more popular as a method to represent solid materials. The DEM is very computationally expensive, but has properties that make it amenable to acceleration by reconfigurable computing. This paper describes the implementation of a dedicated hardware architecture for the DEM implemented on an FPGA, which is capable of giving a speed-zip of about 30 times compared to an optimised software version running on a fast microprocessor.

Speech recognition is a computationally demanding task, particularly the stages which use Viterbi decoding for converting pre-processed speech data into words or subword unit, and the associated observation probability calculations, which employ multivariate Gaussian distributions; so any device that can reduce the load on, for example, a PC's processor, is advantageous. Hence we present two implementations of a speech recognition system incorporating an FPGA, employing continuous hidden Markov models (HMMs), and capable of processing three speech files simultaneously. The first uses monophones, and can perform recognition 250 times real time (in terms of average time per observation), as well as outperforming its software equivalent. The second uses biphones and triphones, reducing the speedup to 13 times real time.

An improved method of performing defuzzification has been identified, together with the realisation of this method using analogue current mode circuitry. The circuits are suitable for fabrication in a standard CMOS process. The defuzzification method is based on the Normalisation Locked Loop (NLL) method, with improvements to allow the processing of triangular membership functions whilst ensuring that relative rule weights are preserved. The circuit used to implement this technique is from the family of saturation-mode, square-law circuits proposed by Bult and Wallinga (1987). Results of simulations are presented and discussed.>