Analog pre-processing has been shown to be energy efficient in a wide variety of low-power applications. Reprogrammable analog devices have leveraged this energy efficiency and applied it to a wider application space, but they still require accurate and stable bias currents for proper operation. For single-application devices, it is sufficient to create temperature compensation schemes that apply to a single bias current. But for reprogrammable or reconfigurable platforms which can be used in a variety of applications, temperature compensation must work well over a large range of potential bias currents and for a large number of different components. In this paper, we present temperature compensation for floating-gate transistors in a reconfigurable system which improves performance over a wide range of currents and temperatures.

Floating-gate transistors have found many applications in both analog and digital systems due to their ability to serve as long-term non-volatile memory. When used in programmable analog applications, the charge on the floating gates must be set very precisely, thereby necessitating precise and steady high voltages to generate programming conditions. In this work, we present a regulated charge pump with extremely low output ripple (2charge pump was fabricated in a 0.35μm standard CMOS process. While operating from a 2.5V supply, this charge pump generates regulated voltages up to 10V.

Floating-gate transistors have been used in many systems to add non-volatile memory. By storing a precise amount of charge on the electrically isolated floating gate, these devices can be used in analog applications as programmable current sources. However, manipulating the stored charge must be done with voltage drops that exceed the supply voltage. In this paper, we present a method to program floating-gate transistors using negative voltages - a desirable characteristic that has been previously inhibited by the difficulties of operating selection circuitry at voltages below the substrate potential. We circumvent the need to have selection circuitry operating at negative voltages by using indirectly programmed floating-gate transistors and a circuit that linearizes the programming currents. We also present a charge pump to generate the necessary negative voltages for programming in this configuration.

Many energy constrained devices such as cell-phones and wearable medical devices utilize sparse or bursty signals — signals characterized by relatively short periods of high activity. Traditional Nyquist-Rate converters are an inefficient tool for converting sparse signals, as a great deal of energy is wasted converting portions of the signal with relatively-low information content. Asynchronous sampling methods attempt to circumvent this inefficiency by sampling based upon the characteristics of the signal itself. However, many asynchronous sampling solutions struggle with a robustness/resolution trade-off. In this paper, we present a new paradigm in which a flexible analog frontend is paired with an asynchronous successive approximation data converter and an asynchronous time-to-digital converter. The result of this paradigm is that the system can be adapted to individual applications, allowing specific data points to be targeted and avoiding data conversion inefficiency. The system will be demonstrated along with the example application of measuring the QRS-complex within an ECG waveform. The demonstrated system, fabricated in standard 0.5μm and 0.35μm processes, produces a minimal number of voltage/time pairs required for studying the QRS complex while consuming 5.96μW of static power.

To meet the demanding requirements in the growing area of wireless sensing applications, some sensing platforms have included low-power application-specific hardware to process the sensor data for compression and pre-classification of the relevant information. While this additional hardware can reduce the overall power consumption of the system, a unique hardware solution is required for each application. To diminish this burden, we will demonstrate a reconfigurable analog/mixed-signal sensing platform. At the hardware-level, this platform consists of a reconfigurable integrated circuit containing many commonly used circuit components that can be connected in any configuration to perform sensor interfacing and ultra-low-power signal processing. At the software level, this platform provides a framework for abstracting the underlying hardware. We will demonstrate how our platform allows a developer to create applications ranging from standard sensor interfacing techniques to more complicated intelligent pre-processing and wake-up detection, without the necessity of circuit-level expertise.

The requirements of many wireless sensing applications approach, or even exceed, the limited hardware capabilities of energy-constrained sensing platforms. To achieve such demanding requirements, some sensing platforms have included low-power application-specific hardware---at the expense of generality---to pre-process the sensor data for reduction to only the relevant information. While this additional hardware can save power by reducing the activity of the microcontroller and radio, a unique hardware solution is required for each application, which presents an unrealistic burden in terms of design time, cost, and ease of integration. To diminish these burdens, we present a reconfigurable analog/mixed-signal sensing platform in this work. At the hardware-level, this platform consists of a reconfigurable integrated circuit containing many commonly used signal-processing blocks and circuit components that can be connected in any configuration. At the software level, this platform provides a framework for abstracting this underlying hardware. We demonstrate how to quickly develop new applications on this platform, ranging from standard sensor interfacing techniques to more complicated intelligent pre-processing and wake-up detection. We also demonstrate how to integrate this platform with commonly used wireless sensor nodes and embedded-system platforms.

The limited power budgets of sensor networks necessitate some level of in-network pre-processing to reduce communication overhead. The low power consumption of analog signal processing (ASP) is well-suited for this task. However, the quick adoption of this technology has been restrained by the fact that ASP implementation requires a priori knowledge of the application space. Our solution to this challenge is to enable run-time reconfiguration through the use of a field-programmable analog array (FPAA). In the same way that reconfigurable digital systems allow system designers to change the infrastructure of digital blocks, an FPAA allows an application developer to change the infrastructure of, and even tune, ASP blocks without circuit-level expertise. We will demonstrate that an FPAA can be used to (1) facilitate the use of ASP to reduce power consumption, and to (2) allow run-time reconfigurability to maximize ASP impact.

In-network processing is recommended for many sensor network applications to reduce communication and improve energy efficiency. However, constraints on memory, speed, and energy currently limit the processing capabilities within a sensor network. In this paper, we describe how ultra-low-power analog circuitry can be integrated with sensor nodes to create energy-efficient sensor networks. We present a custom analog front-end which performs spectral analysis at a fraction of the power used by a digital counterpart. We then show that the front-end can be combined with existing sensor nodes to (1) selectively wake up the mote based upon spectral content of the signal, thus increasing battery life without missing interesting events, and to (2) achieve low-power signal analysis using an analog spectral decomposition block, freeing up digital computation resources for higher-level analysis.

In-network processing is recommended for many sensor network applications to reduce communication and improve energy efficiency. However, constraints on memory, speed, and energy currently limit the processing capabilities within a sensor network. By integrating ultra-low-power analog circuitry with sensor nodes, we can reduce the node's power consumption and extend the node's processing capacity. We present a custom analog front-end which performs spectral analysis at a fraction of the power used by a digital counterpart. This front-end has been combined with a TelosB mote to (1) selectively wake up the mote based upon spectral content of the signal, thus increasing battery life without missing interesting events, and to (2) achieve low-power signal analysis using an analog spectral decomposition block, freeing up digital computation resources for higher-level analysis.

The ability to recalibrate a system is an important feature in allowing that system to maintain optimal performance even in the face of new demands placed on that system by environmental changes or even consumers' desires. The use of floating-gate (FG) transistors provides programmability to analog circuitry and, hence, the ability to recalibrate an analog system. If the FG transistors are programmed indirectly by using a second transistor to perform hot-electron injection, then an analog system can be recalibrated and reprogrammed without ever having to take the circuit out of operation. In this paper, we present a technique for adjusting circuit properties while still in operation as well as example circuits in which this run-time programming is conducted.

A model for soil bidirectional reflectance distribution functions in visible and reflective infrared wavelengths is introduced and compared to data acquired in the field. The model is based on the representation of soil surfaces by a collection of opaque spheres sitting on a Lambertian horizontal surface. The model is not sensitive to increases in the sphere area index beyond a value of 0.4. For comparison, soil reflectance factor data were acquired on a tilled field from many view directions and for a range of solar directions. The observed reflectance factor distributions were consistent with those predicted by the function; maximum reflectance occurred in the antisolar direction and reflectance decreased with increasing phase angle. Increasing the surface roughness by different tillage methods did not substantially alter the directional anisotropy of the soil reflectance factors. The model was fit to the data by a nonlinear least-squares procedure.>