This paper presents a classification method for a Computer-Aided Diagnosis (CAD) system in a colorectal magnified Narrow Band Imaging (NBI) endoscopy. For the classification of a histologic findings, we consider an output result of a lesion endoscopic image from a pre-learned Convolutional Neural Network (CNN) as a feature vector and construct a set of Support Vector Machines (SVMs) by learning a set of the CNN feature vectors. In the video images, each frame has appearance changes such as blur, color shift, reflection of light and so on and it affects classification results. To improve the robustness of CAD system, we construct the SVM learned by multiple image sizes data sets so as to adapt to the noise peculiar to the video image. We confirmed that the proposed method achieves higher robustness, stable, and high classification accuracy in the endoscopic video image. The proposed method also can cope with differences in resolution by old and new endoscopes and perform stably with respect to the input endoscopic video image. We evaluated the proposed method on a customizable embedded DSP core implemented into a FPGA based prototyping system.

This paper presents a hardware implementation of a computer-aided diagnosis system that can classify lesions in real time for endoscopic video image. Unlike still images, video images contain many color shifts, blurs, reflections, and so on, a classification method that takes these noises into account is indispensable. In this paper, in the framework of Bag-of-Feature (BoF), we use a pre-learned convolutional Neural Network (CNN) with general images as feature extraction and Support Vector Machine (SVM) as classification. A robust classification method for endoscopic video is proposed by relearning SVM with several sets of endoscopic images. In addition, since CNN and SVM need to perform many multiplication and accumulation (MAC) operations, we implement the hardware system on a customizable DSP, which can be realize at high speed MAC operations and parallel processing with Very Long Instruction Word (VLIW). The prototyped system can be achieved real-time processing on video frame rate (30 fps @ 200 MHz). The proposed system enables not only to classify the presence or absence of cancer in the lesion but also to identify the progress of cancer and shows the clinical doctor as an objective indicator of the lesion in real time during the endoscopy examination.

In this paper, the computer-aided diagnosis system for colorectal endoscopic images is proposed. The proposed system is consisted of Convolutional Neural Network (CNN) as the feature extraction processing and Support Vector Machine (SVM) as identification processing. The proposed system is also implemented on customizable Digital Signal Processing (DSP) core: Vision P6 DSP and is demonstrated the effectiveness of a real-time recognition system by a FPGA based prototyping system, Protium™ S1.

We are going to develop an ultra-small nutrients analyzer, a compact 3D-monitor (shape, color, etc.), and an ultra-light environment sensor (light intensity, temperature, humidity, CO2, etc.), which can be installed near plants. Accordingly, plant growth estimation technologies based on micro-fluidic circuit model simulating plant vascular system are being developed. The model will be frequently corrected by using updated data given by those sensors. Furthermore, by making use of the estimation technologies, we try to find out suitable cultivation condition for producing plants having aimed characters. In this paper, in order to develop plant growth estimation technologies, we propose a method to analyze the growth of lettuce leaves and roots by image analysis based on visible and thermography thermal imagers captured by cameras in real time and non-destructive leaf and root growth in lettuce hydroponic culture.

BACKGROUND AND OBJECTIVE: A computer-aided system for colorectal endoscopy could provide endoscopists with important helpful diagnostic support during examinations. A straightforward means of providing an objective diagnosis in real time might be for using classifiers to identify individual parts of every endoscopic video frame, but the results could be highly unstable due to out-of-focus frames. To address this problem, we propose a defocus-aware Dirichlet particle filter (D-DPF) that combines a particle filter with a Dirichlet distribution and defocus information. METHODS: We develop a particle filter with a Dirichlet distribution that represents the state transition and likelihood of each video frame. We also incorporate additional defocus information by using isolated pixel ratios to sample from a Rayleigh distribution. RESULTS: We tested the performance of the proposed method using synthetic and real endoscopic videos with a frame-wise classifier trained on 1671 images of colorectal endoscopy. Two synthetic videos comprising 600 frames were used for comparisons with a Kalman filter and D-DPF without defocus information, and D-DPF was shown to be more robust against the instability of frame-wise classification results. Computation time was approximately 88ms/frame, which is sufficient for real-time applications. We applied our method to 33 endoscopic videos and showed that the proposed method can effectively smoothen highly unstable probability curves under actual defocus of the endoscopic videos. CONCLUSION: The proposed D-DPF is a useful tool for smoothing unstable results of frame-wise classification of endoscopic videos to support real-time diagnosis during endoscopic examinations.

This paper describes a novel compact hardware oriented algorithm and its conceptual implementation for real-time traffic signs detection system. The speed limit sign area on a grayscale video frame is detected based on a novel, simple and compact rectangle pattern matching and circle detection modules. The speed limit recognition system is divided into two-pipeline stages. The region of interests is detected by global features of sign and implemented in pipeline, while the speed limit is recognized by local features of numbers. It achieves 100% in sign detection rate and be able to implement on Xilinx SoC Zynq system for real-time processing.

In this study, we have proposed an improvement for feature extraction in computer-aided diagnosis (CAD) system for colorectal endoscopic images with narrow-band imaging (NBI) magnification. Dense Scale-Invariant Feature Transform (D-SIFT) is used in the feature extraction. It is necessary to consider a trade-off between the precision of the feature extraction and speedup by the FPGA implementation for processing of real time full high definition image. In this paper, we reduced the number of dimensions for feature representation in hardware implementation purpose.

The purpose of this research is development of an algorithm for hardware implementation for number recognition applying in speed traffic-sign recognition system for car driving assistant. We recognize the speed limit of the speed traffic-sign using hardware oriented extraction algorithm. The numbers are recognized by comparing their feature values with the recognized features. The proposed hardware oriented number recognition algorithm achieves almost 100 % in recognition rate in 31 scenes in highways and 23 scenes in local roads.

In this study, we perform a device evaluation from trial device production (a computer simulation) using technology CAD (TCAD) in an integrated circuit consistent education system, which consists of a series of processes: system design, semiconductor process, trial device production, and device evaluation. By changing the device parameters (kinds of material, film thickness, impurities density) of the semiconductor process, the simulation can more closely approximate the electrical property of the desired target performance. By integrating the simulation technology using TCAD with each piece of knowledge mastered by the integrated circuit consistent education system, which is currently under development, we are able to construct an education system that can be mastered not only for an integrated circuit for information processing but also for the semiconductor process and the global perspective of the device structure in a power device. Furthermore, the possibility of applicability to a new device structure and process development is shown by means of a simulation using TCAD in virtual processing conditions.

This paper proposes a method for smoothing the posterior probabilities obtained from classification results of time series input. We deal with this problem as a filtering problem with Dirichlet distribution and develop a particle filtering for this task. As a practical example of smoothing, we apply the proposed method to stabilizing NBI endoscopy recognition results over time. Experimental results demonstrate that our approach can effectively smooth highly unstable probability curves.

This paper reports an efficient discrete cosine transform (DCT) processing for the JPEG algorithm using a massive-parallel memory-embedded SIMD matrix processor. The matrix-processing engine has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. For compatibility with this matrix-processing architecture, the conventional DCT algorithm has been improved in arithmetic order and the vertical/horizontal-space 1 dimensional (1D)-DCT processing has been further developed. Evaluation results of the matrix-engine-based DCT processing show that the necessary clock cycles per image blocks can be reduced by 87% in comparison to a conventional DSP architecture. The determined performances in MOPS and MOPS/mm are factors 8 and 5.6 better than with a conventional DSP, respectively. Moreover, the matrix-processing engine can reduce the number of total clock cycles for JPEG application about 49% in comparison to a conventional DSP architecture.

A novel algorithm for object tracking of video pictures, based on image segmentation and pattern matching as well as its FPGA/ASIC implementation architecture are presented. With image segmentation, we can detect all objects in the images no matter whether they are moving or not. Using image segmentation results of successive frames, we exploit pattern matching in a simple object feature space for tracking of objects. The proposed algorithm can be applied to multiple moving and still objects even in the case of a moving camera. The FPGA/ASIC implementation architecture is verified to enable real-time tracking of up to 220 objects, when realized with modern FPGA hardware.

In this paper we propose a learning OCR system which is based on taking a short and long-term memory and a ranking mechanism which manages the transition of reference patterns between two memories. Also, an optimization algorithm is used to optimize the reference vectors magnitude as well as their distribution, continuously. The system was implemented in the FPGA platform and was tested with some real test data of Roman fonts and the classification results found acceptable. LSI architecture Comparing to other learning models like neural networks or A-means, the main advantage of the proposed algorithm is its simple design which makes it implementable in the hardware especially LSI architecture with no need to a large amount of resources.

This paper presents a real-time multi-object tracking architecture based on image segmentation and object matching and its FPGA/ASIC implementation. With image segmentation, we can detect all objects in the image no matter whether they are moving or not. Using image segmentation results of successive frames, we exploit object matching in a simple object feature space for tracking of objects. For both real-time processing and compact implementation, we developed a novel image-scan based region-growing segmentation architecture, which efficiently utilizes high access-bandwidth embedded memories. The structure of image-scan processing element array is at the same time exploited for object feature extraction. Using simple object features, object matching can be realized for finding the most similar object in the previous image frame. The proposed architecture is realized with modern FPGA hardware and is verified to enable real-time tracking of up to 230 objects for QVGA-size video picture at 20MHz clock frequency

We designed a cell-network-based video segmentation test-chip in 0.35μm CMOS technology including a power reduction technique which activates only boundary cells of currently grown regions. The effectiveness of the proposed technique is confirmed by measurement results for a 41x33-sized cell-network, with 23μsec segmentation time (avg.) and 45.8mW power-dissipation (avg.) at 10MHz clock frequency.

We propose a hardware design for parametric active contour models particularly applicable for implementation of gradient vector flow (GVF) snakes. A numerical iterative algorithm of GVF is used to develop a parallel hardware design in a FPGA architecture which is based on using a number of parallel cell units for snake points and a main controller for all control tasks and memory accesses. Using this parallel architecture we could obtain a snake adaptation time of 22 ms in QVGA image size (320/spl times/240 pixels) which was used for motion detection in video samples of 20 fps. The performance results are very encouraging, however, the system can be still improved by using more parallel architecture and simplifying some complicated instructions.

A fully-parallel minimum Hamming-distance search memory has been designed, which uses digital circuitry for bit-comparison and fast analog circuitry for word-comparison as well as winner-take-all (WTA) functionality. The approach allows compact and high-performance integration in conventional CMOS technology. The 0.6μm, 2-poly, 3-metal CMOS design with 32 rows and 128 columns achieves <100ns search times at <260 mW power dissipation. The approach is extendable to increased pattern length and larger row numbers and enables high efficiency for pattern-matching applications such as network routers, code-book-based data compression, or object recognition. As for conventional memories high yield can be achieved with a redundancy concept for rows (including WTA function) and columns.

In the high performance VLSI with multi-layer layout model, the complexity of the global routing problem becomes much high under timing constraints.This paper presents a hierarchical global routing method based on a multi-layer routing model for the high performance standard cell layout.In each hierarchical level, the routes of nets are determined by solving a linear programming problem considering wire-sizing and bufferinsertion under timing constraints.We have implemented the proposed method on a workstation and showed the effectiveness of the method from experimental results.

No abstract available.

In this paper, we propose an adaptive genetic algorithm (GA) to solve the floorplanning problem in VLSI layout design, in which the sequence-pair representation is adopted as the coding scheme of each chromosome. New genetic operators for the problem are presented to explore the search space efficiently. The proposed GA has an adaptive strategy which dynamically selects an appropriate genetic operator during the GA execution depending on the stare of an individual. Experimental results show the effectiveness of our adaptive genetic algorithm compared to simulated annealing (SA).

In this paper, we propose a genetic algorithm (GA) to solve the rectangular packing problem (RP), in which the sequence-pair representation is adopted as the coding scheme of each chromosome. New genetic operators for RP are presented to explore the search space efficiently. The proposed GA has an adaptive strategy which dynamically selects an appropriate genetic operator during the GA execution depending on the state of an individual. Experimental results show the effectiveness of our adaptive genetic algorithm compared to simulated annealing (SA).

This paper describes an LSI implementation of a genetic algorithm (GA), called the Genetic Algorithm Accelerator (GAA) chip. The GAA chip is an LSI implementation of a GA, in which two types of crossover operators are supported, and the operator to be actually used in the algorithm is not fixed in advance, but dynamically selected for each pair of chromosomes in the algorithm execution. The GAA chip has been designed with the Verilog HDL and simulated with some benchmark functions. According to the simulation, the GAA chip will run with a maximum 50 MHz clock. The chip has been fabricated with CMOS 0.5 /spl mu/m standard cell technology.

This paper presents a timing-driven global routing algorithm based on coarse pin assignment, block reshaping, and positioning for VLSI building block layout. As opposed to conventional approaches, we combine pin assignment and global routing problems into one problem. The proposed algorithm determines global routes, coarse pin assignments, and block shape and positions so as to minimize the chip area and total wire length of nets under the given timing constraints. It is based on an iterative improvement paradigm and performs rip-up and rerouting, block reshaping, and positioning in the manner of simulated evolution taking shapes of soft blocks and routing congestion into consideration until the solution is not improved. The Elmore delay model is adopted for the interconnection delay model. Experimental results show the effectiveness of the proposed algorithm.

In this paper, we present a parallel algorithm running on a shared memory multi-processor workstation for timing driven standard cell layout. The proposed algorithm is based on POPINS2.0 and consists of three phases. First, we get an initial placement by a hierarchical timing-driven mincut placement algorithm. At the top level of partitioning hierarchy, we perform one step of bi-partitioning by several processors, and in the lower levels of partitioning hierarchy, partitionings of each region in a level are performed in parallel. Next, in phase 2, iterative improvement of the sub-circuit which contains critical paths is performed by nonlinear programming. Parallel processing is realized by performing the nonlinear programming method to each sub-circuit in parallel. Finally, in phase 3, the placement is transformed to a row based layout style by a timing-driven row assignment method. We have implemented the proposed method on a 4CPU multi-processor workstation and showed that the proposed method is promising through experimental results.

In this paper, we will consider global routing and pin assignment in VLSI building block layout, and present an efficient algorithm which integrates global routing, pin assignment, block reshaping and positioning. The general flow of the proposed algorithm is the same as the one proposed in by Cong in 1991 [1] and consists of two main phases. The first phase is to determine not only global routes and coarse pin assignment in the same way as [1], but also shapes and positions of blocks. The second phase is to compute the final pin assignment for channels. We generalize the channel pin assignment (CPA) problem in [1], in which the CPA problem is formulated for only channels formed by two blocks, to the CPA problem for channels formed by multiple blocks. We will propose a linear time optimal channel pin assignment algorithm, which is an extension of the algorithm in [1]. Experimental results show the effectiveness of the proposed algorithm.

No abstract available.

In this paper, we present a new performance driven placement method based on path delay constraint approach for large standard cell layout. The proposed method consists of three phases and uses the Elmore delay model to model interconnection delay precisely in each phase. In the first phase, initial placement is performed by an efficient performance driven mincut partitioning method. Next, an iterative improvement method by nonlinear programming improves the layout. The improvement is formulated as the problem of minimizing the total wire length subject to critical path delays. Finally, row assignment considering timing constraint is performed. From the experimental results, the proposed method is much better than RITUAL in point of the maximal violation ratio, the total wire length, and the cut size, and is more effective in the interconnection delay model and its extendability.

No abstract available.

This paper presents an MCM routing algorithm considering crosstalk. The aim of the algorithm is to minimize the total wire length under the condition that the crosstalk constraints among nets are satisfied. Experimental results show the effectiveness of the algorithm.

In this paper, we present a formal verification method based on internal variables of a given circuit. In this method, the problem of deciding the logical equivalence of two logic circuits is transformed to the satisfiability problem, which is solved by constructing a set of BDDs, each of which is corresponding to an internal variable of the circuit. Experimental results showed the effectiveness of the proposed method.

In this paper, we propose a heuristic floorplanning method. It is based on tentative insertion of constraints, that intentionally produces redundant constraints to make it possible to search in a wide range of solution space. The proposed method reduces the total area of blocks with the removal and insertion of constraints on the critical path in both horizontal and vertical constraint graphs. Experimental results showed that the quality of solutions of the proposed method is good and even for the large number of blocks, the proposed method keeps a high quality of solution.>

The graph partitioning problem is to partition the vertices of an undirected graph G=(V, E) into two sets of equal size such that the number of edges between them is minimized. In this paper, we propose a systolic algorithm for graph partitioning. The algorithm is based on the Kernighan-Lin heuristic algorithm, runs on a linear array consisting of O(|V|) processing units, and is very suitable for direct VLSI implementation. Computation time of one pass of the proposed algorithm is O(|V|). Simulation experiments showed that the proposed algorithm is as good as the original KL heuristic.>