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Denny D. Tang

dblp:90/3689 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › semiconductor devices
bipolar transistor technology
0.011986
Bipolar trends · Proc. IEEE 1986
Integrated circuit design › semiconductor devices
device scaling
0.011986
Bipolar trends · Proc. IEEE 1986
Integrated circuit design › semiconductor devices › heterojunction bipolar transistor
SiGe HBT
0.011986
Bipolar trends · Proc. IEEE 1986
Integrated circuit design › digital circuit design › logic families
emitter coupled logic
0.011986
Bipolar trends · Proc. IEEE 1986
Integrated circuit design › digital circuit design
high-speed digital circuits
0.011986
Bipolar trends · Proc. IEEE 1986

Methods — techniques the papers use, named apart from their topics

self-aligned structure · 0.0polysilicon emitter contact · 0.0deep-trench isolation · 0.0
YearPublicationVenuePosition
1996 250-600 Mhz 12b digital filters in 0.8-0.25um Bulk and SOI CMOS technologies
abstract
This paper describes a family of high-speed Finite Impulse Response (FIR) digital filters that have been scaled across three generations of CMOS processes. The processes include commercial varieties as well as experimental bulk and low power Silicon-On-Insulator (SOI) technologies. Wafer tests demonstrate the speed and power advantages of the experimental SOI technology when applied to a 24 k-device digital signal processing (DSP) function, by direct comparison with the same filter manufactured in conventional (bulk) CMOS. The filters presented here have 8 taps and operate on 6 b data with 6 b programmable coefficients and deliver 12 b fixed-point output values, but the layout design is modular so that the number of taps and bits can be changed easily. The filters operate with maximal speeds of 250-600 MHz depending on the fabrication technology, and are suitable for the equalization task in Partial Response magnetic recording channels.
Lars E. Thon, Ghavam G. Shahidi, Werner Rausch, Gerald P. Coleman, Denny D. Tang, Dominic Schepis, Ronald Schulz, Fariborz Assadaraghi
ISLPED5
1986 Bipolar trends
abstract
The development of bipolar technology in recent years is reviewed, and trends for future development are projected. The developments clearly point to three salient features of today's advanced bipolar transistors, namely i) self-aligned structure, ii) deeptrench isolation, and iii) polysilicon emitter contact. Both i) and ii) allow advanced bipolar devices to have much higher circuit density and lower power-delay product than without these features. The polysilicon emitter contact allows bipolar devices to be scaled down vertically without suffering from problems of insufficient current gain or low emitter-collector punchthrough voltage. It is clear that while progress will continue in scaling the familiar high-speed ECL logic and memory, the integration level of these very-high-speed chips is severely limited by the accompanied power dissipation. One seemingly promising and yet relatively unexplored direction is to increase the integration level by taking advantage of circuits with much lower power-delay product than ECL, such as NTL, TTL, CIVIL, and MTL to improve the functional throughput. The technology challenges as well as the potential of submicrometer bipolar technology are also discussed.
Tak H. Ning, Denny D. Tang
Proc. IEEE2