This work-in-progress innovative practice paper describes programming mistakes commonly made by students in an introductory embedded systems course and explains them using an antipattern framework. Students in introductory programming courses make mistakes in their code resulting in compile-time and run-time errors that may be difficult to understand as novice programmers. Error messages and debugging tools may not offer much help to novice programmers. Recent work in programming education is using language-specific antipatterns to characterize common errors. Antipatterns (mistakes or errors) can be identified in student code, and students then receive tutorial-oriented feedback to explain the error in terms familiar to them from the course. Software tools are automating the process of providing feedback to students about antipatterns found in their code. In this paper, we describe the study being conducted to identify and classify common antipatterns in C code written by students in an introductory embedded systems course. Antipattern data are being collected from the literature, inspection of student code, and instructor, teaching assistant, and student observations and interviews. Relevant and understandable feedback for each antipattern is also being collected and composed. We are also interested in how antipatterns by students evolve over time, the effect of feedback, and how different development environments support feedback to students. This paper summarizes preliminary results of the study, including several embedded C antipatterns, code examples, and feedback. This work has the potential to improve embedded system teaching and learning. The focus on novice programmers highlights the need for specialized educational tools for this group of students and the potential to further personalize individual learning.

This Innovative Practice Full Paper describes case studies from an instructional design process based on design thinking, illustrating tools used during stages of design. Instructional teams investigated the potential relevance of design thinking in engineering course design in electrical and computer engineering. Two teams of educators used a design thinking process in the redesign of two computer engineering courses, one in embedded systems and one in computer organization and architecture. The process of applying design thinking methods and tools was led by a facilitator with expertise in design thinking and electrical and computer engineering. The process leveraged specific tools and collaboration. This paper presents examples from each course, focusing on the design thinking tools used by the instructors and team members, highlighting what design thinking looks like when applied in this setting, and giving specific examples. The purpose is to suggest strategies and provide information and guidance for educators to use tools in their own course design efforts.

While it is commonly held that debugging is a critical activity for engineers, particularly computer engineers, it is rarely a core component in engineering curriculum. Often it is either considered an innate skill or one to be developed indirectly through coursework. We argue that debugging is more authentically a constellation of mindsets or intrinsic beliefs, values, and dispositions that orient behavior. We define the debugging mindset, describe a series of activities to support the development of such a mindset, and offer evidence of a debugging mindset among students in two computer engineering project courses.

This paper presents findings on participants of a massive open online course named "Educational Robotics for all" developed under Open edX platform. The document describes the organization and structure of the MOOC and some of its preliminary results. As an example, Module 2 about Gender and STEAM is presented and discussed.

This Research-to-Practice Full Paper describes the implementation of integrated reflective activities in two computer engineering courses. Reflective activities contribute to student learning and professional development. Instructional team members have been examining the need and opportunities to deepen learning by integrating reflective activities into problem-solving experiences. We implemented reflective activities using a coordinated framework for a modified Kolbian cycle. The framework consists of reflection-for-action, reflection-in-action, reflection-on-action, and composted reflections. Reflection-for-action takes place before the experience and involves thinking about and planning future actions. Reflection-in-action takes place during the experience while actively problem-solving. Reflection-on-action takes place after the problem-solving experience. Composting involves revisiting past experiences and reflections to inform future planning. We describe the reflective activities in the context of the coordinated framework, including strategies to support reflection and increase the likelihood of engagement and success. We conclude with an analysis of the activities using the CPREE framework for reflection pathways.

This workshop invites discussion about peer review of journal manuscripts in the field of engineering education. The aim is to generate advice for reviewers on how to make effective reviews, which can help editors make appropriate decisions and support authors in improving their manuscripts. The workshop is facilitated by editors of three leading engineering education journals.

This Research-to-Practice Full Paper presents the redesign of a course project to promote student professional formation in engineering in the Electrical and Computer Engineering Department at Iowa State University. This is part of a larger effort to redesign core courses in the sophomore and junior years through a collaborative instructional model and pedagogical approaches that promote professional formation. A required sophomore course on embedded computer systems has been assessed and revised over multiple semesters. The redesign of the project was initiated with the purpose of promoting student professional formation, interest, autonomy and innovation, and it was undertaken using a collaborative process. This paper describes the course, final project, redesign process, assessment, results and future work. Several conclusions from the research may be useful to other educators. A small change to the course project yielded positive effects in interest and autonomy and may influence longer term effects of the project. There was evidence of difference in engagement with the project. The difference observed was not only due to option selected by students but why students selected the option.

This Innovative Practice Full Paper presents a student experience model being implemented in the Electrical and Computer Engineering (ECE) Department at Iowa State University. The department has been implementing, adapting and enhancing a student experience model as part of a scholarship program designed to support and increase the success of students from underrepresented groups in the fields of electrical, computer, software, and cyber security engineering, including community college transfer students. The student experience model uses evidence-based practices focused on professional and leadership development. Interventions include a weekly seminar; group activities such as outreach projects and volunteering; conference participation; faculty and peer mentoring; academic and social support; and collaborative activities with diversity programs, learning communities, student organizations, and companies. Feedback from students and input from peer mentors have been used to improve programming with an emphasis on sense of belonging, professional development, supportive community, leadership, and holistic well-being. In addition, due in part to various entry points into the model, the wide variety of student backgrounds, needs and experiences has been illuminated. This has helped the department and faculty become more aware of issues and consider new models and structures. This paper provides an overview of the student experience model and outcomes, including a summary of research results.

Supervised learning is the workhorse for regression and classification tasks, but the standard approach presumes ground truth for every measurement. In real world applications, limitations due to expense or general infeasibility due to the specific application are common. In the context of agriculture applications, yield monitoring is one such example where simple physics-based measurements such as volume or force-impact have been used to quantify mass flow. These measurements incur error due to sensor calibration. Using a vision system capturing images of a sugarcane elevator and running bamboo under controlled testing as a surrogate material to harvesting sugarcane, mass is accurately predicted from sparsely labeled images by training a deep neural network (DNN) in semi-supervised fashion using only final load weights. The DNN succeeds in capturing the complex density physics of random stacking of slender rods as part of the mass prediction model, and surpasses older volumetric-based methods for mass prediction. Furthermore, by incorporating knowledge about the system physics through the DNN architecture and penalty terms, improvements in prediction accuracy and stability as well as faster learning are obtained. It is shown that the classic nonlinear regression optimization can be reformulated with an aggregation term with some independence assumptions to achieve this feat. Since the number of images for any given run are too large to fit on typical GPU vRAM, an implementation is shown that compensates for the limited memory but still achieve fast training times. The same approach presented herein could be applied to other applications like yield monitoring on grain combines or other harvesters using vision or other instrumentation.

Today's engineers' needs are evolving rapidly as the information and technologies that compete for their attentions. At the same time, our institutions and systems are stretched to their limits to keep up with the changing demands of the times. There is, especially, a need to sustain reflective integration of social and technical knowledge into the future generations of engineering, to make engineers more humane, in order for them to generate technological solutions that are more human-centric. Addressing such needs requires new approaches to teaching and designing engineering courses. Any advancement in the education sector from here forward requires a new thinking paradigm that can be applied in large-scale systematic reform of education: design thinking. This paper outlines means to use design thinking as the foundational methodology for transforming a traditional electrical and computer engineering department into an agile department where design thinking, systems thinking, professional skills and inclusion are promoted, and collaborative, inquiry-driven processes are stimulated to create and sustain new ways of thinking, interacting, teaching, learning and working.

The percentages of women in undergraduate electrical and computer engineering programs at Iowa State University averages below the national average. An external assessment of diversity and inclusion provided an impetus for faculty, staff and administrators to discuss issues, focus on specific areas, and collaborate on planning. In particular, the department has teamed up with the university's Program for Women in Science and Engineering to better integrate their programs with departmental activities. This has resulted in an enhanced student experience model being designed for undergraduate ECE women. The model leverages effective practices including learning communities, leadership and professional development, academic support and advising for the ISU Engineering Basic Program, academic preparation for the ECE field, and state and national resources for inclusive ECE career awareness, recruiting and teaching. The WI-ECSEL Initiative has been designed to improve diversity and inclusion in Iowa State's electrical, computer, and software engineering programs; improve educational pathways including transfer transitions from community colleges; provide a supportive and integrated student experience; establish a community of practice for faculty; and use research to inform practice.

Graphics Processing Units (GPUs) have become a prevalent platform for high throughput general purpose computing. The peak computational throughput of GPUs has been steadily increasing with each technology node by scaling the number of cores on the chip. Although this vastly improves the performance of several compute-intensive applications, our experiments show that some applications can achieve peak performance without utilizing all cores on the chip. We refer to the number of cores at which performance of an application saturates as the optimal number of active cores (Nopt). We propose executing the application on Noptcores, and power-gating the unused cores to reduce static power consumption. Towards this target, we present ONAC (Optimal Number of Active Cores detector), a runtime technique to detect Nopt. ONAC uses a novel estimation model, which significantly reduces the number of hardware samples taken to detect the optimal core count, compared to a sequential detection technique (Seq-Det). We implement ONAC and Seq-Det in a cycle-level GPU performance simulator and analyze their effect on performance, power and energy. Our evaluation shows that ONAC and Seq-Det can reduce energy consumption by 20% and 10% on average for memory-intensive applications, without sacrificing more than 2% performance. The higher energy savings for ONAC comes from reducing the detection time by 45% as compared to Seq-Det.

Graphics Processing Units (GPUs) have been widely adopted as accelerators for high performance computing due to the immense amount of computational throughput they offer over their CPU counterparts. As GPU architectures are optimized for throughput, they execute a large number of SIMD threads (warps) in parallel and use hardware multithreading to hide the pipeline and memory access latencies. While the Two-Level Round Robin (TLRR) and Greedy Then Oldest (GTO) warp scheduling policies have been widely accepted in the academic research community, there is no consensus regarding which policy works best for all applications. In this paper, we show that the disparity regarding which scheduling policy works better depends on the characteristics of instructions in different regions (phases) of the application. We identify these phases at compile time and design a novel warp scheduling policy that uses information regarding them to make scheduling decisions at runtime. By mitigating the adverse effects of application phase behavior, our policy always performs closer to the better of the two existing policies for each application. We evaluate the performance of the warp schedulers on 35 kernels from the Rodinia and CUDA SDK benchmark suites. For applications that have a better performance with the GTO scheduler, our warp scheduler matches the performance of GTO with 99.2% accuracy and achieves an average speedup of 6.31% over RR. Similarly, for applications that perform better with RR, the performance of our scheduler is within of 98% of RR and achieves an average speedup of 6.65% over GTO.

The flipped classroom model is gaining increasing attention in higher education, including engineering education. There are various types of models and contexts in which they are applied. Generalized research on the effectiveness of the flipped classroom is emerging, and results have been mixed. One such model is team-based learning (TBL) as originally developed by Larry Michaelsen in the late 1970s. TBL is a structured way to implement a flipped classroom approach, and has been shown to be successful in achieving deeper learning among the students. In this paper, we discuss our experience using the TBL methodology in a graduate computer engineering course on system level design of embedded systems. Specifically, we describe the course design, instructor experience adapting TBL for use in the course, including implementing an asynchronous online TBL process, and instructor reflections and student feedback on what worked well and what did not. We analyze the course content using the Florida Taxonomy of Cognitive Behavior, and assess the effectiveness of our implementation in achieving deeper learning. Additionally, we report on student perception of the new course structure and their experience using TBL.

We have investigated whether Agile practices can be applied as a pedagogical approach to derive benefit in the areas of encouraging students to take responsibility for their learning (self managed learning), continuous improvement through reflection, alternative approaches for grading, increased engagement by learners, and more effective data collection and assessment of outcomes. Agile is an umbrella term for values, principles and practices applied to the process of software development. The Agile movement has aimed to develop a new and better culture within the software development community and has seen an increased rate of adoption within corporate settings. The goal of this workshop is to help participants explore how Agile development, a management technique borne out of the software industry, can not only change the way that students engage in project-based and team-based course projects, but also transform the way that we educate our students.

Professional skills are often emphasized in a capstone engineering design course, especially in relation to addressing ABET Engineering Criteria. Learning of these skills is typically a product of the project management approach followed by design teams. The principles behind agile development and the features of the Scrum methodology match up well with the expected outcomes of a major engineering design experience and preparation needed by students for engineering practice. This paper presents a case study on design team use of an agile process for the successful development and release on the Google Play store of an Android app for a client during the span of a two-semester senior design course in electrical and computer engineering. The agile project management used in the case study was found to be beneficial to all involved (students, mentors, and clients). It emphasizes behaviors that lead to greater satisfaction and higher quality results with the senior design experience. Student learning opportunities related to professional skills are examined. This work adds to emerging literature promoting agile development as a model for capstone projects.

College-level online learning took off in a big way in 2012, and is likely to impact every department and teacher in some manner. This workshop will highlight major developments in online education technology in engineering and computer science. The workshop will highlight recent online trends like flipped classrooms and MOOCs, will survey various authoring and delivery platforms like EdX and Zyante, summarize some research on online/flipped teaching, discuss methods for instructors to collaborate on delivering instructional experiences, and highlight experiences by teachers of online and hybrid courses.

An NSF Scholarships in STEM (S-STEM) program has provided scholarships for cohorts of undergraduate engineering students since 2009, giving specific attention to the National Academy of Engineering's vision for the engineer of 2020 (E2020). Four E2020 outcomes are emphasized in Iowa State's program: leadership, global awareness and understanding, systems thinking, and innovation and entrepreneurship. These outcomes, or pillars, are being integrated into curricular and co-curricular activities. The four pillar areas are introduced in a one-semester first-year seminar and reinforced in a two-semester second-year seminar. These seminars supplement the regular program of study for engineering students. In this paper, we describe the curriculum and its planned integration beyond the scholarship program. We present student feedback about their experience in the program. We also introduce relevant core competencies associated with the outcomes as judged by faculty and industry representatives.

The number of active threads required to achieve peak application throughput on graphics processing units (GPUs) depends largely on the ratio of time spent on computation to the time spent accessing data from memory. While compute-intensive applications can achieve peak throughput with a low number of threads, memory-intensive applications might not achieve good throughput even at the maximum supported thread count. In this paper, we study the effects of scheduling work from multiple applications on the same GPU core. We claim that interleaving workload from different applications on a GPU core can improve the utilization of computational units and reduce the load on memory subsystem. Experiments on 17 application pairs from the Rodinia benchmark suite show that overall throughput increases by 7% on average.

The E2020 Scholars Program is a National Science Foundation Scholarships in STEM (S-STEM) Program providing scholarships for cohorts of first-year and transfer undergraduate engineering students. The conceptual framework of the E2020 Scholars Program is designed to advance the academic and professional development of the scholar using the college's learning community infrastructure and building upon the aspirations and attributes of the National Academy of Engineering's (NAE) vision for the engineer of 2020. Programming includes a set of student development and learning opportunities consistent with this vision and includes curricular and co-curricular activities on the topics of leadership development, global awareness and understanding, systems thinking, and innovation.

This paper reviews the framework and provides new result for the implementation of a new program designed to develop more effective future faculty in engineering. The core of the proposed program will be based on our efforts regarding the recently developed Minor in Engineering Studies (MES). This program will team up effective engineering faculty to train, mentor, and evaluate a select group of graduate students to teach classes in our MES program. The goal is to help the engineering graduate students (the graduate educators) become better communicator and better educators by training non-engineering students in technological literacy classes. This practice is being introduced as a possible venue to develop and enhance the effectiveness of the graduate educators as classroom instructors and that therefore this is the way to train effective future faculty in engineering. This paper will introduce new results, and describe the new findings and developments in this project. In this paper we introduce the conceptual framework of the MES and the results of the early implementation of this study.

A combination of Web services and ontology technologies has a potential to provide a consistent, seamless, and intelligent integration of heterogeneous resources. Using these technologies, we present a new visualization framework which integrates distributed and heterogeneous performance information into system-level visualizations. Most performance visualization tools often are specific to a particular resource at a certain level of the system, possibly with fixed views. Thus, they limit a user's ability to observe a performance problem associated with multiple resources across platforms and semantic levels. Addressing this issue with Web services and ontology, the new framework allows resources, at different levels, to be viewed and interacted with in a consistent and coordinated manner. This paper describes our framework, focusing on how Web services and ontology help address challenging issues in performance visualization for grid environments

Abstract A new software technology for on‐line performance analysis and the visualization of complex parallel and distributed systems is presented. Often heterogeneous, these systems need capabilities for the flexible integration and configuration of performance analysis and visualization. Our technology is based on an object‐oriented framework for the rapid prototyping and development of distributable visual objects. The visual objects consist of two levels, a platform/device‐specific low level and an analysis‐ and visualization‐specific high level. We have developed a very high‐level markup language called VOML and a compiler for the component‐based development of high‐level visual objects. The VOML is based on a software architecture for on‐line event processing and performance visualization called EPIRA. The technology lends itself to constructing high‐level visual objects from globally distributed component definitions. Details of the technology and tools used, as well as how an example visual object can be rapidly prototyped from several reusable components, are presented. Copyright © 2003 John Wiley & Sons, Ltd.

Assessing the performance of complex systems is important but difficult for all users in every phase of a system lifespan. Current performance analysis tools have proven successful but have not been widely used outside the laboratory. Laboratory-oriented analyses, queries and views, and rigid, insufficiently documented tool architectures create this situation. This paper presents a framework for addressing these limitations, including multiple abstraction level analysis and an open software architecture to address these limitations. An examination of this framework illustrates its capabilities for varied analysis environments and users.

Researchers and practitioners in the area of parallel and distributed computing have been lacking a portable, flexible and robust distributed instrumentation system. This paper presents the reference implementation of Baseline Reduced Instrumentation System Kernel (BRISK). BRISK was developed as a part of a realtime system instrumentation and performance visualization project. The design is based on a simple distributed instrumentation system model for flexibility and extensibility. The basic implementation poses minimalistic system requirements and achieves high performance. The paper also shows evaluations of BRISK on both basic and advanced configurations. The first evaluation emphasizes local, simple performance metrics; and the second highlights aggregate performance, built-in clock synchronization and dynamic on-line sorting. Copyright © 2000 John Wiley & Sons, Ltd.

This paper demonstrates the use of a model-based evaluation approach for instrumentation systems (ISs). The overall objective of this study is to provide early feedback to tool developers regarding IS overhead and performance; such feedback helps developers make appropriate design decisions about alternative system configurations and task scheduling policies. We consider three types of system architectures: network of workstations (NOW), symmetric multiprocessors (SMP), and massively parallel processing (MPP) systems. We develop a Resource OCCupancy (ROCC) model for an on-line IS for an existing tool and parameterize it for an IBM SP-2 platform. This model is simulated to answer several "what if" questions regarding two policies to schedule instrumentation data forwarding: collect-and-forward (CF) and batch-and-forward (BF). In addition, this study investigates two alternatives for forwarding the instrumentation data: direct and binary tree forwarding for an MPP system. Simulation results indicate that the BF policy can significantly reduce the overhead and that the tree forwarding configuration exhibits desirable scalability characteristics for MPP systems. Initial measurement-based testing results indicate more than 60 percent reduction in the direct IS overhead when the BF policy was added to Paradyn parallel performance measurement tool.

A page layout segmentation algorithm for locating text, background and halftone areas is presented. The algorithm has been implemented on Splash 2-an FPGA-based array processor. The speed as determined by the Xilinx synthesis tools projects an application speed of 5 MHz. For documents of size 1,024/spl times/1,024 pixels, a significant speedup of two orders of magnitude compared to a SparcStation 20 has been achieved.

This paper presents a case study of modeling, evaluating, and testing the data collection services (called an instrumentation system) of the Paradyn parallel performance measurement tool using well-known performance evaluation and experiment design techniques. The overall objective of the study is to use modeling- and simulation-based evaluation to provide feedback to the tool developers to help them choose system configurations and task scheduling policies that can significantly reduce the data collection overheads. We develop and parameterize a resource occupancy (ROCC) model for Paradyn instrumentation system (IS) for an IBM SP-2 platform. This model is parameterized with a measurement-based workload characterization and subsequently used to answer several "what if" questions regarding configuration options and two policies to schedule instrumentation system tasks: collect-and-forward (CF) and batch-and-forward (BF) policies. Simulation results indicate that the BF policy can significantly reduce the overheads. Based on this feedback, the BF policy was implemented in Paradyn IS as an option to manage the data collection. Measurement-based testing results obtained from this enhanced version of Paradyn IS are reported in this paper and indicate more than 60% reduction in the direct IS overheads when the BF policy is used.

Convolution is a fundamental operation in many signal and image processing applications. Since the computation and communication pattern in a convolution operation is regular, a number of special architectures have been designed and implemented for this operator. The Von Neumann architectures cannot meet the real-time requirements of applications that use convolution as an intermediate step. We combine the advantages of systolic algorithms with the low cost of developing application specific designs using field programmable gate arrays (FPGAs) to build a scalable convolver for use in computer vision systems. The performance of the systolic algorithm of (Kung et al., 1981) is compared theoretically and experimentally with many other convolution algorithms reported in the literature. The implementation of a convolution operation on Splash 2, an attached processor based on Xilinx 4010 FPGAs, is reported with impressive performance gains.

Software instrumentation is a widely used technique for parallel program performance evaluation, debugging, steering, and visualization. With increasing sophistication of parallel tool development technologies and broadening of application areas where these tools are being used, runtime data collection and management activities are growing in importance; we use the term instrumentation system (IS) to refer to components that support these activities in state-of-the-art parallel tool environments. An IS consists of Local Instrumentation Servers, an Instrumentation System Manager, and a Transfer Protocol. The overheads and perturbation effects attributed to an IS must be accounted for to ensure correct and efficient representation of program behavior, especially for on-line and real-time environments. Moreover, an IS is a key facilitator of integration of tools in an environment. In this paper, we define the primary components of an IS and their roles in an integrated environment, and classify ISs according to selected features. We introduce a structured approach to plan, design, model, evaluate, implement, and validate an IS. The approach provides a means to formally address domain-specific requirements. The modeling and evaluation processes are illustrated in the context of three distinctive IS case studies for PICL, Paradyn, and Vista. Valuable feedback on performance effects of IS parameters and policies can assist developers in making design decisions early in the software development cycle. Additionally, use of structured software engineering methods can support the mapping of an abstract IS model to an implementation of the IS.

The techniques and tools that have been developed for the performance evaluation of parallel and distributed computing systems are manifold. This is appealing, since no single technique or tool will be sufficient. However there is a lack of integration of tools in the form of environments and frameworks, which hinders the development of well-defined methodologies for obtaining optimal performance and answering users' performance questions. This roundtable considers the issues surrounding tool integration and interoperability. Perhaps the dominant issue is whether this area is mature enough for prescribed frameworks to be successfully implemented and consistently adhered to: should the focus be on making sure each tool works, or can it shift to making sure tools can work together? The participants address the advantages and disadvantages, practicalities, recent history, and future of tool integration in high-performance computing.>

Scalability has become an important consideration in parallel algorithm and machine designs. The word scalable, or scalability, has been widely and often used in the parallel processing community. However, there is no adequate, commonly accepted definition of scalability available. Scalabilities of computer systems and programs are difficult to quantify, evaluate, and compare. In this paper, scalability is formally defined for algorithm-machine combinations. A practical method is proposed to provide a quantitative measurement of the scalability. The relation between the newly proposed scalability and other existing parallel performance metrics is studied. A harmony between speedup and scalability has been observed. Theoretical results show that a large class of algorithm-machine combinations is scalable and the scalability can be predicted through premeasured machine parameters. Two algorithms have been studied on an nCUBE 2 multicomputer and on a MasPar MP-1 computer. These case studies have shown how scalabilities can be measured, computed, and predicted. Performance instrumentation and visualization tools also have been used and developed to understand the scalability related behavior.>

The user of a parallel computer system would like to know the performance of a program in terms of how optimally it uses the system resources. This task is increasingly performed by program performance visualization. The limitations of conventional performance data analysis techniques necessitate better visual analysis methods that are scalable with the problem and system sizes and extensible. They should represent some physical and logical structure of the parallel system and program. The analysis techniques presented here have been motivated by the use of signal and (two- and three-dimensional) image processing techniques being applied in some areas of scientific visualization. Results of applying selected techniques are shown. These techniques and tools have advantages and disadvantages when applied in this area.>