Steven Balensiefer

dblp:90/4493 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
2 papers
Concurrent programming · 80% Compilers and program optimization · 20%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Concurrent programming
memory models
0.112007
Enforcing isolation and ordering in STM · PLDI 2007
Concurrent programming › transactional memory
software transactional memory
0.112007
Enforcing isolation and ordering in STM · PLDI 2007
Concurrent programming
transactional memory
0.112007
Enforcing isolation and ordering in STM · PLDI 2007
Compilers and program optimization › domain-specific compilation
quantum compilation
0.112005
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures · ISCA 2005
Emerging computing paradigms
quantum computer architecture
0.112005
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures · ISCA 2005
Emerging computing paradigms › quantum computer architecture
trapped ion quantum computer
0.112005
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures · ISCA 2005
Emerging computing paradigms › quantum computer architecture
fault-tolerant quantum computing
0.012005
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures · ISCA 2005

Methods — techniques the papers use, named apart from their topics

microarchitecture evaluation · 0.1compilation and simulation framework · 0.1
YearPublicationVenuePosition
2008 Practical weak-atomicity semantics for java stm
abstract
As memory transactions have been proposed as a language-level replacement for locks, there is growing need for well-defined semantics. In contrast to database transactions, transaction memory (TM) semantics are complicated by the fact that programs may access the same memory locations both inside and outside transactions. Strongly atomic semantics, where non transactional accesses are treated as implicit single-operation transactions, remain difficult to provide without specialized hardware support or significant performance overhead. As an alternative, many in the community have informally proposed that a single global lock semantics [18,10], where transaction semantics are mapped to those of regions protected by a single global lock, provide an intuitive and efficiently implementable model for programmers.
Vijay Menon 0002, Steven Balensiefer, Tatiana Shpeisman, Ali-Reza Adl-Tabatabai, Richard L. Hudson, Bratin Saha, Adam Welc
SPAA2
2007 Enforcing isolation and ordering in STM
abstract
Transactional memory provides a new concurrency control mechanism that avoids many of the pitfalls of lock-based synchronization. High-performance software transactional memory (STM) implementations thus far provide weak atomicity: Accessing shared data both inside and outside a transaction can result in unexpected, implementation-dependent behavior. To guarantee isolation and consistent ordering in such a system, programmers are expected to enclose all shared-memory accesses inside transactions.
Tatiana Shpeisman, Vijay Menon 0002, Ali-Reza Adl-Tabatabai, Steven Balensiefer, Dan Grossman, Richard L. Hudson, Katherine F. Moore, Bratin Saha
PLDI4
2005 An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures
abstract
The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical implementation technology has progressed steadily. However, almost no work has yet been done which explores the architecture design space of large scale quantum computing systems. In this paper, we present a set of tools that enable the quantitative evaluation of architectures for quantum computers. The infrastructure we created comprises a complete compilation and simulation system for computers containing thousands of quantum bits. We begin by compiling complete algorithms into a quantum instruction set. This ISA enables the simple manipulation of quantum state. Another tool we developed automatically transforms quantum software into an equivalent, fault-tolerant version required to operate on real quantum devices. Next, our infrastructure transforms the ISA into a set of low-level micro architecture specific control operations. In the future, these operations can be used to directly control a quantum computer. For now, our simulation framework quickly uses them to determine the reliability of the application for the target micro architecture. Finally, we propose a simple, regular architecture for ion-trap based quantum computers. Using our software infrastructure, we evaluate the design trade offs of this micro architecture.
Steven Balensiefer, Lucas Kreger-Stickles, Mark Oskin
ISCA1