Machine-to-Machine (M2M) wireless communication requires the transmission of short blocks of data with high reliability over fading channels. We discuss the use of the probabilistic data association (PDA) detector in conjunction with precoding to design high-performance systems for these links. First, the performance of the traditional PDA algorithm with precoding over ideal Rayleigh fading links is analyzed, which provides insight into its performance, and evidence of an error floor at high SNRs. Then, a novel ordering mechanism is proposed that takes advantage of the precoder characteristics. It is shown by simulation that the proposed modified algorithm can achieve near-ML performance for block sizes as small as 32 symbols.

It has been shown that the secrecy capacity of a wireless network is pushed rapidly towards zero as the number of users in the network grows. To deal with this issue, a secure method which intentionally superposes precoded jamming signals has been proposed. In this paper, we analyze its advantage to realize a secure wireless network in the presence of a large number (e.g., hundreds) of eavesdropping users, for transmitting confidential messages. Our analysis and simulations demonstrate that the jamming superposition achieves high secrecy rate even for undesired cases where the channels for many eavesdroppers are noise-less and highly correlated with the intended receiver.

Block transmission with cyclic prefix is a promising technique to realize high-speed data rates in frequency-selective fading channels. Many popular linear precoding schemes, including orthogonal frequency-division multiplexing (OFDM), single-carrier (SC) block transmission, and time-reversal (TR), can be interpreted as such a block transmission. This paper presents a unified performance analysis that shows how the optimal precoding strategy depends on the optimization criterion such as capacity, mean-square error, and secrecy. We analyze three variants of TR methods (based on maximum-ratio combining, equal-gain combining and selective combining) and two-types of pre-equalization methods (zero-forcing and minimum mean-square error). As one application of our framework, we derive optimal precoding (i.e., OFDM with optimal power and phase control) in the presence of interference limitation for distributed antenna systems; we find that without power/phase control, OFDM does not have any capacity advantage over SC transmissions. When comparing SC and TR, we verify that for single-antenna systems in the high SNR regimes, SC has a capacity advantage; however, TR performs better in the low SNR regime. For distributed multiple-antenna systems, TR always provides higher capacity, and the capacity of TR can approach that of optimal precoders with a large number of distributed antennas. Furthermore, we make an analysis of secrecy capacity which shows how high-rate messages can be transmitted towards an intended user without being decoded by the other users from the viewpoint of information-theoretic security. We demonstrate that TR precoding can be the best candidate among the non-optimal precoders for achieving high secrecy capacity, while the optimal precoder offers a significant gain over those non-optimal precoders.

Two of the major challenges facing OFDM/OFDMA systems are their sensitivity to frequency selective fading and ICI due to CFO or Doppler shift, especially when the subcarrier spacing becomes smaller. We propose an OFDM transceiver design that employs frequency redundant subcarrier mapping to mitigate frequency selective fading and subcarrier spreading to achieve ICI self cancellation. Both our theoretical analysis and simulation show that such a code-spread-interleaved-redundant OFDM system design offers significant (over 10 dB) improvement in CIR and robust BER performance in different channel conditions.

Interconnect delay has become a limiting factor for circuit performance in deep sub-micrometer designs. As the crosstalk in an on-chip bus is highly dependent on the data patterns transmitted on the bus, different crosstalk avoidance coding schemes have been proposed to boost the bus speed and/or reduce the overall energy consumption. Despite the availability of the codes, no systematic mapping of datawords to codewords has been proposed for CODEC design. This is mainly due to the nonlinear nature of the crosstalk avoidance codes (CAC). The lack of practical CODEC construction schemes has hampered the use of such codes in practical designs. This work presents guidelines for the CODEC design of the “forbidden pattern free crosstalk avoidance code” (FPF-CAC). We analyze the properties of the FPF-CAC and show that mathematically, a mapping scheme exists based on the representation of numbers in the Fibonacci numeral system. Our first proposed CODEC design offers a near-optimal area overhead performance. An improved version of the CODEC is then presented, which achieves theoretical optimal performance. We also investigate the implementation details of the CODECs, including design complexity and the speed. Optimization schemes are provided to reduce the size of the CODEC and improve its speed.

In this work, we present a CODEC design for the forbidden transition free crosstalk avoidance code. Our mapping and coding scheme is based on the Fibonacci numeral system and the mathematical analysis shows that all numbers can be represented by FTF vectors in the Fibonacci numeral system (FNS). The proposed CODEC design is highly efficient, modular and can be easily combined with a bus partitioning technique. We also investigate the implementation issues and our experimental results show that the proposed CODEC complexity is orders of magnitude better compared to the brute force implementation. Compared to the best existing approaches, we achieve a 17% improvement in logic complexity. A high speed design can be achieved through pipelining.

We propose two crosstalk reducing coding schemes using ternary busses. In addition to low power consumption and reduced delay, our schemes offer other advantages over binary coding schemes such as zero area overhead and simple, regular and fast codec design.

In this paper, we investigate the low-complexity synchronization design for multi-band orthogonal-frequency-division-multiplexing (MB-OFDM) ultra-wideband (UWB) systems. We propose a unified synchronizer design based on auto-correlation-function. The key component in the proposed synchronizer is a parallel signal detector structure in which multiple auto-correlation units are instantiated and their outputs are shared by other functional units in the synchronizer, including time-frequency pattern detection, symbol timing, carrier frequency offset estimation and correction and frame synchronization. We show that, via analysis and simulations, such a design achieves not only a low computation cost which makes it attractive in implementation, but also equal or better performance compared to the cross-correlation based designs.

Low power consumption is a critical issue in many UWB systems. This paper investigates the application of dynamic voltage scaling (DVS) and other low power design techniques to a multiband-OFDM UWB transceiver baseband circuit design in order to reduce average power consumption of the chip. The results show significant power savings over the conventional approach.

In recent times, the ratio of the cross-coupling capacitance between adjacent on-chip wires on the same metal layer to the total capacitance of any wire is becoming quite large. As a consequence, signal wires exhibit a significant delay variation and noise immunity problems. This problem is aggravated for long on-chip buses. In this paper, we develop memory-based crosstalk canceling CODECs for on-chip buses. We describe an reduced ordered binary decision diagram (ROBDD) based methodology to accurately compute the bus area overhead of the CODECs. We report the asymptotic overhead for CODECs which cancel three kinds of crosstalk patterns, and demonstrate that the bus size overheads are lower than the corresponding overheads for a memoryless CODEC. This results in a reduced overall area utilization for memory-based crosstalk canceling CODECs, compared to their memoryless counterparts. We also demonstrate that the use of these crosstalk canceling CODECs enables a user to speed up a bus by a factor of over 6/spl times/. Further, by using our techniques, a user may trade off the speed gain against the attendant bus size overhead.

In recent times, much attention has been devoted to power optimization for real-time systems, while guaranteeing that such systems meet their hard (or soft) scheduling deadlines. To reduce power, different tasks in such systems may be run at different power supply voltages, in order to maximally utilize slack in the schedule. However, prior approaches have ignored the practical aspects of switching the power supply. In a typical IC, the VDD net is highly capacitive, and as a result, its voltage cannot be changed instantaneously. In traditional approaches, the assumption is that this net switches instantaneously, which in effect makes it essential to include the VDD switching time in the worst-case execution time (WCET) of a process (adding pessimism to the WCET value). In our approach, we precisely model the switching of the VDD net, and allow the system to continue computations while VDD is being switched. The effect on the delay of tasks during this transition is precisely modeled. This allows a designer to obtain more realistic estimates of the WCET of a process, reducing the pessimism inherent in real-time system scheduling. Our approach can be implemented as a simple look-up table in a real-time scheduler. Our experimental results show that our model is highly accurate, with an error of <0.2% compared to SPICE simulations.

In modern VLSI processes, the cross-coupling capacitance between adjacent neighboring wires on the same metal layer is a very large fraction of the total wire capacitance. This leads to problems of delay variation due to crosstalk and reduced noise immunity, arguably one of the biggest obstacles in the design ICs in recent times. This problem is particularly severe in long on-chip buses, since bus signals are routed at minimum pitch for long distances. In this work, we propose to solve this problem by the use of crosstalk canceling CODECs. We only utilize memoryless CODECs, to reduce the logical complexity and enhance the robustness of our techniques. Bus data patterns can be classified (as 4/spl middot/C, 3/spl middot/C, 2/spl middot/C, 1/spl middot/C or 0/spl middot/C patterns) based on the maximum amount of crosstalk that they can exhibit. Crosstalk avoidance CODECs which eliminate 4/spl middot/C and 3/spl middot/C patterns have been reported. In this paper, we describe crosstalk avoidance techniques which eliminate 2/spl middot/C and 1/spl middot/C patterns. We describe an analytical methodology to accurately characterize the bus area overhead 2/spl middot/C pattern CODECs. Using these results, we characterize the area overhead versus crosstalk immunity achieved. A similar exercise is performed for 1/spl middot/C patterns. Our experimental results show that by using 2/spl middot/C crosstalk canceling techniques, buses can be sped up by up to a factor of 6 with an area overhead of about 200%, and that 1/spl middot/C techniques are not very robust.